diff --git a/Max10_VGA/Max10_VGA.qsf b/Max10_VGA/Max10_VGA.qsf
index 3f143bb..a1d4c10 100644
--- a/Max10_VGA/Max10_VGA.qsf
+++ b/Max10_VGA/Max10_VGA.qsf
@@ -45,7 +45,6 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk12m
 
 
 set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name SYSTEMVERILOG_FILE vga_testbench.sv
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_acc.tcl
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_button.tcl
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_gpio.tcl
@@ -55,4 +54,12 @@ set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_ram.tcl
 set_global_assignment -name SDC_FILE timings.sdc
 set_global_assignment -name QIP_FILE PLL.qip
 set_global_assignment -name SYSTEMVERILOG_FILE top.sv
+set_global_assignment -name SYSTEMVERILOG_FILE top_tb.sv
+set_global_assignment -name SYSTEMVERILOG_FILE vga_controller.sv
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb -section_id tb
+set_global_assignment -name EDA_TEST_BENCH_FILE top_tb.sv -section_id tb
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Max10_VGA/Max10_VGA.qws b/Max10_VGA/Max10_VGA.qws
new file mode 100644
index 0000000..e81da79
Binary files /dev/null and b/Max10_VGA/Max10_VGA.qws differ
diff --git a/Max10_VGA/top.sv b/Max10_VGA/top.sv
index 7e88d00..1a294a3 100644
--- a/Max10_VGA/top.sv
+++ b/Max10_VGA/top.sv
@@ -1,77 +1,24 @@
 module top (
 	// Main 12M clock
 	input logic clk12m,
-
-	// Accelerometer
-	output logic acc_sclk,
-	output logic acc_mosi,
-	input  logic acc_miso,
-	output logic acc_cs,
-	input  logic acc_int1,
-	input  logic acc_int2,
-
-	// Onboard button
-	input  logic btn,
-
 	// Header GPIO
 	inout  logic [14:0] gpio_d,
-	input  logic  [7:0] gpio_a,
-
 	// Onboard LEDs
-	output logic  [8:1] led,
-
-	// PMOD header
-	inout  logic  [8:1] pmod,
-
-	// Onboard RAM
-	output logic        ram_clk,
-	inout  logic [15:0] ram_data,
-	output logic [13:0] ram_addr,
-	output logic  [1:0] ram_dqm,
-	output logic  [1:0] ram_bs,
-	output logic        ram_cke,
-	output logic        ram_ras,
-	output logic        ram_cas,
-	output logic        ram_we,
-	output logic        ram_cs
+	output logic  [8:1] led
 );
-
 	wire pixel_clk;
 	
 	PLL p_clk_pll (clk12m, pixel_clk);
 	
-	wire h_sync, v_sync;
-	assign gpio_d[13] = h_sync;
-	assign gpio_d[12] = v_sync;
+	wire vsync_pulse, hsync_pulse;
 	
-	reg [9:0] h_counter;
-	reg [9:0] v_counter;
-	
-	// VGA 640 x 480 @ 60 Hz
-	// pixel_clk 25.175MHz
-	always @(posedge pixel_clk) begin
-		if (h_counter < 799) begin
-			h_counter <= h_counter + 1;
-		end else begin
-			// reset scanline
-			h_counter <= 1'b0;
-			
-			// step v_counter after hline
-			if (v_counter < 524) begin
-				v_counter <= v_counter + 1;
-			end else begin
-				v_counter <= 1'b0;
-			end
-		end
-	end
-	
-	// generate sync pulses
-	assign h_sync = (h_counter < 96) ? 1'b1 : 1'b0;
-	assign v_sync = (v_counter < 2) ? 1'b1 : 1'b0;
-	
-	assign led[1] = h_sync;
-	assign led[2] = v_sync;
-	assign led[3] = pixel_clk;
-	assign led[8:4] = v_counter;
+	VGA_Controller controller(
+		.pixel_clk(pixel_clk),
+		.h_sync(hsync_pulse),
+		.v_sync(vsync_pulse)
+	);
+
+	assign v_sync = gpio_d[12];
+	assign h_sync = gpio_d[13];
 
 endmodule
diff --git a/Max10_VGA/top_tb.sv b/Max10_VGA/top_tb.sv
new file mode 100644
index 0000000..fb380bc
--- /dev/null
+++ b/Max10_VGA/top_tb.sv
@@ -0,0 +1,24 @@
+`timescale 1 ns / 100 ps
+
+module tb();
+	reg clk = 1'b0;
+	
+	wire v_h_sync;
+	wire v_v_sync;
+	
+	VGA_Controller VGA_Controller_Inst(
+		.pixel_clk(clk),
+		.h_sync(v_h_sync),
+		.v_sync(v_v_sync)
+	);
+
+	// 25MHz clock
+	always #5 clk <= ~clk;
+	
+	initial begin
+		$display($time, " Starting the Simulation");
+		#1000
+		$finish();
+	end
+	
+endmodule
diff --git a/Max10_VGA/top_tb.sv.bak b/Max10_VGA/top_tb.sv.bak
new file mode 100644
index 0000000..8ec50bd
--- /dev/null
+++ b/Max10_VGA/top_tb.sv.bak
@@ -0,0 +1,24 @@
+`timescale 1 ns / 100 ps
+
+module tb();
+	reg clk = 1'b0;
+	
+	reg [14:0] v_gpio_d;
+	reg [8:1] v_led;
+	
+	VGA_Controller VGA_Controller_Inst(
+		.pixel_clk(clk),
+		.gpio_d(v_gpio_d)
+	);
+
+	// 25MHz clock
+	always #5 clk <= ~clk;
+	
+	
+	initial begin
+		$display($time, " Starting the Simulation");
+		#1000
+		$finish();
+	end
+	
+endmodule
diff --git a/Max10_VGA/vga_controller.sv b/Max10_VGA/vga_controller.sv
new file mode 100644
index 0000000..da4b465
--- /dev/null
+++ b/Max10_VGA/vga_controller.sv
@@ -0,0 +1,32 @@
+module VGA_Controller(
+	input wire pixel_clk,
+	output wire h_sync,
+	output wire v_sync
+);
+	
+	reg [9:0] h_counter;
+	reg [9:0] v_counter;
+	
+	// VGA 640 x 480 @ 60 Hz
+	// pixel_clk 25.175MHz
+	always @(posedge pixel_clk) begin
+		if (h_counter < 799) begin
+			h_counter <= h_counter + 1;
+		end else begin
+			// reset scanline
+			h_counter <= 1'b0;
+			
+			// step v_counter after hline
+			if (v_counter < 524) begin
+				v_counter <= v_counter + 1;
+			end else begin
+				v_counter <= 1'b0;
+			end
+		end
+	end
+	
+	// generate sync pulses
+	assign h_sync = (h_counter < 96) ? 1'b1 : 1'b0;
+	assign v_sync = (v_counter < 2) ? 1'b1 : 1'b0;
+
+endmodule
diff --git a/Max10_VGA/vga_controller.sv.bak b/Max10_VGA/vga_controller.sv.bak
new file mode 100644
index 0000000..a94004a
--- /dev/null
+++ b/Max10_VGA/vga_controller.sv.bak
@@ -0,0 +1,8 @@
+module VGA_Controller(
+	input wire pixel_clk,
+	inout  logic [14:0] gpio_d,
+	output logic  [8:1] led
+};
+
+
+endmodule