From 0cf72c6c3b6432740e996f64e2dc04d86d2fde5c Mon Sep 17 00:00:00 2001 From: Ben Kyd Date: Mon, 7 Jul 2025 12:11:19 +0100 Subject: [PATCH] TEsting yosys --- .gitignore | 3 +- readme.md => README.md | 0 Verilator_Tests/clk/Makefile | 4 + Verilator_Tests/clk/top.v | 6 + Verilator_Tests/clk/ulx4m.mk | 34 +++ Verilator_Tests/clk/ulx4m_v002.lpf | 397 +++++++++++++++++++++++++++++ 6 files changed, 443 insertions(+), 1 deletion(-) rename readme.md => README.md (100%) create mode 100644 Verilator_Tests/clk/Makefile create mode 100644 Verilator_Tests/clk/top.v create mode 100644 Verilator_Tests/clk/ulx4m.mk create mode 100644 Verilator_Tests/clk/ulx4m_v002.lpf diff --git a/.gitignore b/.gitignore index e475577..19e09b8 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,4 @@ Blink/ max1000_template/ - +build/ +bin/ diff --git a/readme.md b/README.md similarity index 100% rename from readme.md rename to README.md diff --git a/Verilator_Tests/clk/Makefile b/Verilator_Tests/clk/Makefile new file mode 100644 index 0000000..169f930 --- /dev/null +++ b/Verilator_Tests/clk/Makefile @@ -0,0 +1,4 @@ +VERILOG = top.v +DEVICE = um-45k + +include ./ulx4m.mk diff --git a/Verilator_Tests/clk/top.v b/Verilator_Tests/clk/top.v new file mode 100644 index 0000000..f2ec373 --- /dev/null +++ b/Verilator_Tests/clk/top.v @@ -0,0 +1,6 @@ +module top ( + input clk_25mhz, + output [3:0] led +); + assign led[0] = clk_25mhz; +endmodule diff --git a/Verilator_Tests/clk/ulx4m.mk b/Verilator_Tests/clk/ulx4m.mk new file mode 100644 index 0000000..2534bb0 --- /dev/null +++ b/Verilator_Tests/clk/ulx4m.mk @@ -0,0 +1,34 @@ +PIN_DEF ?= ./ulx4m_v002.lpf + +DEVICE ?= 85k + +BUILDDIR = bin + +TOP ?= top + +compile: $(BUILDDIR)/toplevel.bit + +prog: $(BUILDDIR)/toplevel.bit + fujprog $^ + +dfu: $(BUILDDIR)/toplevel.bit + dfu-util -a 0 -D $^ -R + +$(BUILDDIR)/toplevel.json: $(VERILOG) + mkdir -p $(BUILDDIR) + yosys \ + -p "read -sv $^" \ + -p "hierarchy -top ${TOP}" \ + -p "synth_ecp5 -abc9 -json $@" \ + +$(BUILDDIR)/%.config: $(PIN_DEF) $(BUILDDIR)/toplevel.json + nextpnr-ecp5 --${DEVICE} --package CABGA381 --timing-allow-fail --freq 25 --textcfg $@ --json $(filter-out $<,$^) --lpf $< + +$(BUILDDIR)/toplevel.bit: $(BUILDDIR)/toplevel.config + ecppack --compress $^ $@ + +clean: + rm -rf ${BUILDDIR} + +.SECONDARY: +.PHONY: compile clean prog diff --git a/Verilator_Tests/clk/ulx4m_v002.lpf b/Verilator_Tests/clk/ulx4m_v002.lpf new file mode 100644 index 0000000..3208109 --- /dev/null +++ b/Verilator_Tests/clk/ulx4m_v002.lpf @@ -0,0 +1,397 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +## ULX4M-LS v0.0.2 + +# The clock "usb" and "gpdi" sheet +LOCATE COMP "clk_25mhz" SITE "G2"; +IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk_25mhz" 25 MHZ; + +# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash +# write to FLASH possible any time from JTAG: +# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE; +# write to FLASH possible from user bitstream: +SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; + +## LED indicators "blinkey" and "gpio" sheet +LOCATE COMP "led[3]" SITE "C1"; +LOCATE COMP "led[2]" SITE "B3"; +LOCATE COMP "led[1]" SITE "B1"; +LOCATE COMP "led[0]" SITE "B2"; +IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Buttons "blinkey" and "gpio" sheet +LOCATE COMP "btn[1]" SITE "C3"; +LOCATE COMP "btn[2]" SITE "C2"; +IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI Flash chip "flash" sheet +LOCATE COMP "flash_csn" SITE "R2"; +LOCATE COMP "flash_clk" SITE "U3"; +LOCATE COMP "flash_mosi" SITE "W2"; +LOCATE COMP "flash_miso" SITE "V2"; +LOCATE COMP "flash_holdn" SITE "W1"; +LOCATE COMP "flash_wpn" SITE "Y2"; +#LOCATE COMP "flash_csspin" SITE "AJ3"; +#LOCATE COMP "flash_initn" SITE "AG4"; +#LOCATE COMP "flash_done" SITE "AJ4"; +#LOCATE COMP "flash_programn" SITE "AH4"; +#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; +#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; +#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; +IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SD card "sdcard", "usb" sheet +LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14 CM4_GPIO12 +LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi_GPIO15 CM4_GPIO27 +LOCATE COMP "sd_d[0]" SITE "J3"; # sd_dat0_do (MISO) WiFi_GPIO2 CM4_GPIO4 +LOCATE COMP "sd_d[1]" SITE "H1"; # sd_dat1_irq WiFi_GPIO4 CM4_GPIO3 +LOCATE COMP "sd_d[2]" SITE "K1"; # sd_dat2 WiFi_GPIO12 CM4_GPIO2 +LOCATE COMP "sd_d[3]" SITE "K2"; # sd_dat3_csn WiFi_GPIO13 CM4_GPIO14 +LOCATE COMP "sd_wp" SITE "P5"; # not connected +LOCATE COMP "sd_cdn" SITE "N5"; # not connected +IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement +IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "sd_pwr_on" SITE "U17"; # J2_5- GN14 +IOBUF PORT "sd_pwr_on" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Second USB port "US2" going directly into FPGA "usb", "ram" sheet +LOCATE COMP "usb_fpga_dp" SITE "E16"; # same on ULX3S and ULX4M +LOCATE COMP "usb_fpga_dn" SITE "F16"; # same on ULX3S and ULX4M +IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16; +IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16; +LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # single-ended bidirectional same on ULX3S and ULX4M +LOCATE COMP "usb_fpga_bd_dn" SITE "E15"; # single-ended bidirectional same on ULX3S and ULX4M +IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "usb_fpga_pu_dp" SITE "A2"; # pull up/down control +LOCATE COMP "usb_fpga_pu_dn" SITE "A3"; +IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +LOCATE COMP "usb_fpga_otg_id" SITE "A4"; +IOBUF PORT "usb_fpga_otg_id" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "n_extrst" SITE "U16"; +IOBUF PORT "n_extrst" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## JTAG ESP-32 "usb" sheet +# connected to FT231X and ESP-32 +# commented out because those are dedicated pins, not directly useable as GPIO +# but could be used by some vendor-specific JTAG bridging (boundary scan) module +#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives +#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits +#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives +#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives +#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SDRAM "ram" sheet +LOCATE COMP "sdram_clk" SITE "G19"; +LOCATE COMP "sdram_cke" SITE "G20"; +LOCATE COMP "sdram_csn" SITE "P18"; +LOCATE COMP "sdram_wen" SITE "N20"; +LOCATE COMP "sdram_rasn" SITE "M18"; +LOCATE COMP "sdram_casn" SITE "N18"; +LOCATE COMP "sdram_a[0]" SITE "L19"; +LOCATE COMP "sdram_a[1]" SITE "L20"; +LOCATE COMP "sdram_a[2]" SITE "M19"; +LOCATE COMP "sdram_a[3]" SITE "H17"; +LOCATE COMP "sdram_a[4]" SITE "F20"; +LOCATE COMP "sdram_a[5]" SITE "F18"; +LOCATE COMP "sdram_a[6]" SITE "E19"; +LOCATE COMP "sdram_a[7]" SITE "F19"; +LOCATE COMP "sdram_a[8]" SITE "E20"; +LOCATE COMP "sdram_a[9]" SITE "C20"; +LOCATE COMP "sdram_a[10]" SITE "N19"; +LOCATE COMP "sdram_a[11]" SITE "D20"; +LOCATE COMP "sdram_a[12]" SITE "E18"; +LOCATE COMP "sdram_ba[0]" SITE "L18"; +LOCATE COMP "sdram_ba[1]" SITE "M20"; +LOCATE COMP "sdram_dqm[0]" SITE "P20"; +LOCATE COMP "sdram_dqm[1]" SITE "D19"; +LOCATE COMP "sdram_d[0]" SITE "U20"; +LOCATE COMP "sdram_d[1]" SITE "T20"; +LOCATE COMP "sdram_d[2]" SITE "U19"; +LOCATE COMP "sdram_d[3]" SITE "T19"; +LOCATE COMP "sdram_d[4]" SITE "T18"; +LOCATE COMP "sdram_d[5]" SITE "T17"; +LOCATE COMP "sdram_d[6]" SITE "R20"; +LOCATE COMP "sdram_d[7]" SITE "P19"; +LOCATE COMP "sdram_d[8]" SITE "H20"; +LOCATE COMP "sdram_d[9]" SITE "J19"; +LOCATE COMP "sdram_d[10]" SITE "K18"; +LOCATE COMP "sdram_d[11]" SITE "J18"; +LOCATE COMP "sdram_d[12]" SITE "H18"; +LOCATE COMP "sdram_d[13]" SITE "J16"; +LOCATE COMP "sdram_d[14]" SITE "K19"; +LOCATE COMP "sdram_d[15]" SITE "J17"; +IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +# GPDI differential interface (Video) "gpdi" sheet +LOCATE COMP "gpdi_dp[0]" SITE "F17"; # Blue + +LOCATE COMP "gpdi_dn[0]" SITE "G18"; # Blue - +LOCATE COMP "gpdi_dp[1]" SITE "D18"; # Green + +LOCATE COMP "gpdi_dn[1]" SITE "E17"; # Green - +LOCATE COMP "gpdi_dp[2]" SITE "C18"; # Red + +LOCATE COMP "gpdi_dn[2]" SITE "D17"; # Red - +LOCATE COMP "gpdi_dp[3]" SITE "J20"; # Clock + +LOCATE COMP "gpdi_dn[3]" SITE "K20"; # Clock - +#LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet + +#LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet - +LOCATE COMP "gpdi_cec" SITE "A18"; +#LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC +#LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12 +IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +LOCATE COMP "gpdi_dp[4]" SITE "B9"; # Blue + +#LOCATE COMP "gpdi_dn[4]" SITE "C10"; # Blue - +LOCATE COMP "gpdi_dp[5]" SITE "A7"; # Green + +#LOCATE COMP "gpdi_dn[5]" SITE "A8"; # Green - +LOCATE COMP "gpdi_dp[6]" SITE "C8"; # Red + +#LOCATE COMP "gpdi_dn[6]" SITE "B8"; # Red - +LOCATE COMP "gpdi_dp[7]" SITE "B11"; # Clock + +#LOCATE COMP "gpdi_dn[7]" SITE "C11"; # Clock - +IOBUF PORT "gpdi_dp[4]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[4]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[5]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[5]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[6]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[6]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[7]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[7]" IO_TYPE=LVCMOS33D DRIVE=4; + +# wifi - do not use together with CM4 GPIO +LOCATE COMP "wifi_gpio0" SITE "U1"; +LOCATE COMP "wifi_gpio2" SITE "K4"; # sd_d0_do (MISO) WiFi GPIO2 +LOCATE COMP "wifi_gpio4" SITE "J5"; # sd_d1_irq WiFi GPIO4 +LOCATE COMP "wifi_gpio5" SITE "U5"; # +LOCATE COMP "wifi_gpio12" SITE "K5"; # sd_d2 WiFi_GPIO12 +LOCATE COMP "wifi_gpio13" SITE "L4"; # sd_d3_csn WiFi_GPIO13 +LOCATE COMP "wifi_gpio14" SITE "L5"; # sd_clk WiFi_GPIO14 +LOCATE COMP "wifi_gpio15" SITE "N16"; # sd_cmd_di (MOSI) WiFi GPIO15 +LOCATE COMP "wifi_gpio19" SITE "P4"; +LOCATE COMP "wifi_gpio21" SITE "P17"; +LOCATE COMP "wifi_gpio22" SITE "P16"; +LOCATE COMP "wifi_gpio25" SITE "L16"; +LOCATE COMP "wifi_gpio26" SITE "N17"; +LOCATE COMP "wifi_gpio27" SITE "G16"; +LOCATE COMP "wifi_gpio33" SITE "H16"; +LOCATE COMP "wifi_gpio34" SITE "V4"; +LOCATE COMP "wifi_gpio35" SITE "N17"; + +IOBUF PORT "wifi_gpio0" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio2" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # pull down or drive 0 for esp32 programming +IOBUF PORT "wifi_gpio4" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio5" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio12" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio13" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # pull down or drive 0 for esp32 programming +IOBUF PORT "wifi_gpio14" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio15" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio19" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio21" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio22" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio25" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio26" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio27" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio33" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio34" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio35" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +LOCATE COMP "ftdi_txden" SITE "T1"; # FTDI_TXDEN +LOCATE COMP "LED1_HAT" SITE "N5"; # LED1 on HAT +LOCATE COMP "wifi_en" SITE "U18";# WIFI_EN +LOCATE COMP "ftdi_txd" SITE "N4"; # FTDI_TXD +LOCATE COMP "ftdi_rxd" SITE "N3"; # FTDI_RXD +LOCATE COMP "wifi_txd" SITE "P5"; # WIFI_TXD +LOCATE COMP "wifi_rxd" SITE "V1"; # WIFI_RXD + +IOBUF PORT "ftdi_txden" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "LED1_HAT" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ftdi_txd" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ftdi_rxd" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +LOCATE COMP "btn[3]" SITE "E3"; +LOCATE COMP "btn[4]" SITE "E4"; +LOCATE COMP "btn[5]" SITE "E5"; +LOCATE COMP "btn[6]" SITE "H5"; +LOCATE COMP "btn[0]" SITE "H4"; +LOCATE COMP "nc1" SITE "F2"; +LOCATE COMP "sw" SITE "G3"; +IOBUF PORT "btn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "nc1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## CM4 GPIO +LOCATE COMP "gpio[0]" SITE "R16"; # SDA0 - WIFI_GPIO21 +LOCATE COMP "gpio[1]" SITE "R17"; # SCL0 - WIFI_GPIO22 +LOCATE COMP "gpio[2]" SITE "K5"; # SD_D2 - ESP32 SD share +LOCATE COMP "gpio[3]" SITE "J5"; # SD_D1 - ESP32 SD share +LOCATE COMP "gpio[4]" SITE "K4"; # SD_D0 - ESP32 SD share +LOCATE COMP "gpio[5]" SITE "H16"; # WIFI_GPIO33 +LOCATE COMP "gpio[6]" SITE "R1"; # BTN1 on HAT +LOCATE COMP "gpio[7]" SITE "P3"; # BTN2 on HAT +LOCATE COMP "gpio[8]" SITE "P4"; # WIFI_GPIO19 +LOCATE COMP "gpio[9]" SITE "G16"; # WIFI_GPIO27 +LOCATE COMP "gpio[10]" SITE "N17";# WIFI_GPIO26 +LOCATE COMP "gpio[11]" SITE "L16";# WIFI_GPIO25 +LOCATE COMP "gpio[12]" SITE "C4"; # FPGA TDI do not use - not connected! +LOCATE COMP "gpio[13]" SITE "T1"; # FTDI_TXDEN +LOCATE COMP "gpio[14]" SITE "L4"; # SD_D3 - ESP32 SD share +LOCATE COMP "gpio[15]" SITE "L5"; # SD_CLK - ESP32 SD share +LOCATE COMP "gpio[16]" SITE "B4"; # FPGA TDO do not use - not connected! +LOCATE COMP "gpio[17]" SITE "M17";# WIFI_GPIO35 +LOCATE COMP "gpio[18]" SITE "N5"; # LED1 on HAT +LOCATE COMP "gpio[19]" SITE "U1"; # WIFI_GPIO0 +LOCATE COMP "gpio[20]" SITE "E4"; # FPGA TCK do not use - not connected! +LOCATE COMP "gpio[21]" SITE "D5"; # FPGA TMS do not use - not connected! +LOCATE COMP "gpio[22]" SITE "U18";# WIFI_EN +LOCATE COMP "gpio[23]" SITE "N4"; # FTDI_TXD +LOCATE COMP "gpio[24]" SITE "N3"; # FTDI_RXD +LOCATE COMP "gpio[25]" SITE "P5"; # WIFI_TXD +LOCATE COMP "gpio[26]" SITE "V1"; # WIFI_RXD +LOCATE COMP "gpio[27]" SITE "N16";# SD_CMD - ESP32 SD share +IOBUF PORT "gpio[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[16]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[17]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[18]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[19]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[20]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[21]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[22]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[23]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[24]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[25]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[26]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpio[27]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## DSI +# +LOCATE COMP "dsiRX0_dp[0]" SITE "B12"; # Clk + +LOCATE COMP "dsiRX0_dn[0]" SITE "C12"; # Clk - +LOCATE COMP "dsiRX0_dp[1]" SITE "A12"; # DSI RX D0 + +LOCATE COMP "dsiRX0_dn[1]" SITE "A13"; # DSI RX D0 - +LOCATE COMP "dsiRX0_dp[2]" SITE "B13"; # DSI RX D1 + +LOCATE COMP "dsiRX0_dn[2]" SITE "C13"; # DSI RX D1 - +LOCATE COMP "dsiTX0_dp[0]" SITE "D12"; # Clk + +LOCATE COMP "dsiTX0_dn[0]" SITE "E12"; # Clk - +LOCATE COMP "dsiTX0_dp[1]" SITE "D13"; # DSI TX D0 + +LOCATE COMP "dsiTX0_dn[1]" SITE "E13"; # DSI TX D0 - +LOCATE COMP "dsiTX0_dp[2]" SITE "A14"; # DSI TX D1 + +LOCATE COMP "dsiTX0_dn[2]" SITE "C14"; # DSI TX D1 - +IOBUF PORT "dsiRX0_dp[0]" IO_TYPE=LVCMOS12 ; +IOBUF PORT "dsiRX0_dn[0]" IO_TYPE=LVCMOS12 ; +IOBUF PORT "dsiRX0_dp[1]" IO_TYPE=LVCMOS12 ; +IOBUF PORT "dsiRX0_dn[1]" IO_TYPE=LVCMOS12 ; +IOBUF PORT "dsiRX0_dp[2]" IO_TYPE=LVCMOS12 ; +IOBUF PORT "dsiRX0_dn[2]" IO_TYPE=LVCMOS12 ; +IOBUF PORT "dsiTX0_dp[0]" IO_TYPE=LVCMOS12 ; +IOBUF PORT "dsiTX0_dp[0]" IO_TYPE=LVCMOS12 ; +IOBUF PORT "dsiTX0_dp[1]" IO_TYPE=LVCMOS12 ; +IOBUF PORT "dsiTX0_dp[1]" IO_TYPE=LVCMOS12 ; +IOBUF PORT "dsiTX0_dp[2]" IO_TYPE=LVCMOS12 ; +IOBUF PORT "dsiTX0_dp[2]" IO_TYPE=LVCMOS12 ; + +## PROGRAMN (reload bitstream from FLASH, exit from bootloader) +# PCB v2.0.5 and higher +LOCATE COMP "user_programn" SITE "M4"; +IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) +# on PCB v1.7 shutdown is not connected to FPGA +LOCATE COMP "shutdown" SITE "G16"; # FPGA receives +IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;