diff --git a/Max10_Raytracer/.gitignore b/Max10_RT/.gitignore similarity index 100% rename from Max10_Raytracer/.gitignore rename to Max10_RT/.gitignore diff --git a/Max10_Raytracer/Max10_VGA.qpf b/Max10_RT/Max10_RT.qpf similarity index 70% rename from Max10_Raytracer/Max10_VGA.qpf rename to Max10_RT/Max10_RT.qpf index 0622df0..b0932ae 100644 --- a/Max10_Raytracer/Max10_VGA.qpf +++ b/Max10_RT/Max10_RT.qpf @@ -2,4 +2,4 @@ QUARTUS_VERSION = "17.1" DATE = "13:14:16 February 14, 2018" # Revisions -PROJECT_REVISION = "Max10_VGA" +PROJECT_REVISION = "Max10_RT" diff --git a/Max10_Raytracer/Max10_VGA.qsf b/Max10_RT/Max10_RT.qsf similarity index 98% rename from Max10_Raytracer/Max10_VGA.qsf rename to Max10_RT/Max10_RT.qsf index 84abb38..8fe4dda 100644 --- a/Max10_Raytracer/Max10_VGA.qsf +++ b/Max10_RT/Max10_RT.qsf @@ -45,6 +45,12 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk12m set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb -section_id tb +set_global_assignment -name EDA_TEST_BENCH_FILE top_tb.sv -section_id tb set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_acc.tcl set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_button.tcl set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_gpio.tcl @@ -56,11 +62,6 @@ set_global_assignment -name QIP_FILE PLL.qip set_global_assignment -name SYSTEMVERILOG_FILE top.sv set_global_assignment -name SYSTEMVERILOG_FILE top_tb.sv set_global_assignment -name SYSTEMVERILOG_FILE vga_controller.sv -set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation -set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb -section_id eda_simulation -set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation -set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb -set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb -section_id tb -set_global_assignment -name EDA_TEST_BENCH_FILE top_tb.sv -section_id tb set_global_assignment -name SYSTEMVERILOG_FILE vga_test_screen.sv +set_global_assignment -name SYSTEMVERILOG_FILE raytracer.sv set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Max10_RT/Max10_RT.qws b/Max10_RT/Max10_RT.qws new file mode 100644 index 0000000..fc2afee Binary files /dev/null and b/Max10_RT/Max10_RT.qws differ diff --git a/Max10_Raytracer/Max10_VGA_assignment_defaults.qdf b/Max10_RT/Max10_RT_assignment_defaults.qdf similarity index 100% rename from Max10_Raytracer/Max10_VGA_assignment_defaults.qdf rename to Max10_RT/Max10_RT_assignment_defaults.qdf diff --git a/Max10_Raytracer/Max10_VGA_nativelink_simulation.rpt b/Max10_RT/Max10_RT_nativelink_simulation.rpt similarity index 100% rename from Max10_Raytracer/Max10_VGA_nativelink_simulation.rpt rename to Max10_RT/Max10_RT_nativelink_simulation.rpt diff --git a/Max10_Raytracer/PLL.ppf b/Max10_RT/PLL.ppf similarity index 100% rename from Max10_Raytracer/PLL.ppf rename to Max10_RT/PLL.ppf diff --git a/Max10_Raytracer/PLL.qip b/Max10_RT/PLL.qip similarity index 100% rename from Max10_Raytracer/PLL.qip rename to Max10_RT/PLL.qip diff --git a/Max10_Raytracer/PLL.v b/Max10_RT/PLL.v similarity index 100% rename from Max10_Raytracer/PLL.v rename to Max10_RT/PLL.v diff --git a/Max10_Raytracer/PLL_bb.v b/Max10_RT/PLL_bb.v similarity index 100% rename from Max10_Raytracer/PLL_bb.v rename to Max10_RT/PLL_bb.v diff --git a/Max10_Raytracer/PLL_inst.v b/Max10_RT/PLL_inst.v similarity index 100% rename from Max10_Raytracer/PLL_inst.v rename to Max10_RT/PLL_inst.v diff --git a/Max10_Raytracer/pins/assignment_acc.tcl b/Max10_RT/pins/assignment_acc.tcl similarity index 100% rename from Max10_Raytracer/pins/assignment_acc.tcl rename to Max10_RT/pins/assignment_acc.tcl diff --git a/Max10_Raytracer/pins/assignment_button.tcl b/Max10_RT/pins/assignment_button.tcl similarity index 100% rename from Max10_Raytracer/pins/assignment_button.tcl rename to Max10_RT/pins/assignment_button.tcl diff --git a/Max10_Raytracer/pins/assignment_gpio.tcl b/Max10_RT/pins/assignment_gpio.tcl similarity index 100% rename from Max10_Raytracer/pins/assignment_gpio.tcl rename to Max10_RT/pins/assignment_gpio.tcl diff --git a/Max10_Raytracer/pins/assignment_led.tcl b/Max10_RT/pins/assignment_led.tcl similarity index 100% rename from Max10_Raytracer/pins/assignment_led.tcl rename to Max10_RT/pins/assignment_led.tcl diff --git a/Max10_Raytracer/pins/assignment_pmod.tcl b/Max10_RT/pins/assignment_pmod.tcl similarity index 100% rename from Max10_Raytracer/pins/assignment_pmod.tcl rename to Max10_RT/pins/assignment_pmod.tcl diff --git a/Max10_Raytracer/pins/assignment_ram.tcl b/Max10_RT/pins/assignment_ram.tcl similarity index 100% rename from Max10_Raytracer/pins/assignment_ram.tcl rename to Max10_RT/pins/assignment_ram.tcl diff --git a/Max10_RT/raytracer.sv b/Max10_RT/raytracer.sv new file mode 100644 index 0000000..2b19b5d --- /dev/null +++ b/Max10_RT/raytracer.sv @@ -0,0 +1,8 @@ +module Raytracer( + input wire pixel_clk, + input reg [10:0] x, + input reg [10:0] y, + output reg [2:0] rgb +); + +endmodule diff --git a/Max10_RT/raytracer.sv.bak b/Max10_RT/raytracer.sv.bak new file mode 100644 index 0000000..32bae69 --- /dev/null +++ b/Max10_RT/raytracer.sv.bak @@ -0,0 +1,3 @@ +module Raytracer(); + +endmodule diff --git a/Max10_Raytracer/timings.sdc b/Max10_RT/timings.sdc similarity index 100% rename from Max10_Raytracer/timings.sdc rename to Max10_RT/timings.sdc diff --git a/Max10_Raytracer/top.sv b/Max10_RT/top.sv similarity index 100% rename from Max10_Raytracer/top.sv rename to Max10_RT/top.sv diff --git a/Max10_Raytracer/top_tb.sv b/Max10_RT/top_tb.sv similarity index 100% rename from Max10_Raytracer/top_tb.sv rename to Max10_RT/top_tb.sv diff --git a/Max10_Raytracer/vga_controller.sv b/Max10_RT/vga_controller.sv similarity index 100% rename from Max10_Raytracer/vga_controller.sv rename to Max10_RT/vga_controller.sv diff --git a/Max10_Raytracer/vga_test_screen.sv b/Max10_RT/vga_test_screen.sv similarity index 100% rename from Max10_Raytracer/vga_test_screen.sv rename to Max10_RT/vga_test_screen.sv diff --git a/Max10_Raytracer/Max10_VGA.qws b/Max10_Raytracer/Max10_VGA.qws deleted file mode 100644 index 30200da..0000000 Binary files a/Max10_Raytracer/Max10_VGA.qws and /dev/null differ diff --git a/Max10_Raytracer/top.sv.bak b/Max10_Raytracer/top.sv.bak deleted file mode 100644 index 4c76ace..0000000 --- a/Max10_Raytracer/top.sv.bak +++ /dev/null @@ -1,42 +0,0 @@ -module max1000_template ( - // Main 12M clock - input logic clk12m, - - // Accelerometer - output logic acc_sclk, - output logic acc_mosi, - input logic acc_miso, - output logic acc_cs, - input logic acc_int1, - input logic acc_int2, - - // Onboard button - input logic btn, - - // Header GPIO - inout logic [14:0] gpio_d, - input logic [7:0] gpio_a, - - // Onboard LEDs - output logic [8:1] led, - - // PMOD header - inout logic [8:1] pmod, - - // Onboard RAM - output logic ram_clk, - inout logic [15:0] ram_data, - output logic [13:0] ram_addr, - output logic [1:0] ram_dqm, - output logic [1:0] ram_bs, - output logic ram_cke, - output logic ram_ras, - output logic ram_cas, - output logic ram_we, - output logic ram_cs -); - -// This is the top module, enter your design here -// Happy HDL :] - -endmodule diff --git a/Max10_Raytracer/top_tb.sv.bak b/Max10_Raytracer/top_tb.sv.bak deleted file mode 100644 index 8ec50bd..0000000 --- a/Max10_Raytracer/top_tb.sv.bak +++ /dev/null @@ -1,24 +0,0 @@ -`timescale 1 ns / 100 ps - -module tb(); - reg clk = 1'b0; - - reg [14:0] v_gpio_d; - reg [8:1] v_led; - - VGA_Controller VGA_Controller_Inst( - .pixel_clk(clk), - .gpio_d(v_gpio_d) - ); - - // 25MHz clock - always #5 clk <= ~clk; - - - initial begin - $display($time, " Starting the Simulation"); - #1000 - $finish(); - end - -endmodule diff --git a/Max10_Raytracer/vga_controller.sv.bak b/Max10_Raytracer/vga_controller.sv.bak deleted file mode 100644 index a94004a..0000000 --- a/Max10_Raytracer/vga_controller.sv.bak +++ /dev/null @@ -1,8 +0,0 @@ -module VGA_Controller( - input wire pixel_clk, - inout logic [14:0] gpio_d, - output logic [8:1] led -}; - - -endmodule diff --git a/Max10_Raytracer/vga_test_screen.sv.bak b/Max10_Raytracer/vga_test_screen.sv.bak deleted file mode 100644 index 23864f1..0000000 --- a/Max10_Raytracer/vga_test_screen.sv.bak +++ /dev/null @@ -1,5 +0,0 @@ -VGA_Test_Screen( - input wire [10:0] scan_pos_x, - input wire [10:0] scan_pos_y, - output wire [2:0] rgb, -); \ No newline at end of file diff --git a/Max10_VGA/top.sv.bak b/Max10_VGA/top.sv.bak deleted file mode 100644 index 4c76ace..0000000 --- a/Max10_VGA/top.sv.bak +++ /dev/null @@ -1,42 +0,0 @@ -module max1000_template ( - // Main 12M clock - input logic clk12m, - - // Accelerometer - output logic acc_sclk, - output logic acc_mosi, - input logic acc_miso, - output logic acc_cs, - input logic acc_int1, - input logic acc_int2, - - // Onboard button - input logic btn, - - // Header GPIO - inout logic [14:0] gpio_d, - input logic [7:0] gpio_a, - - // Onboard LEDs - output logic [8:1] led, - - // PMOD header - inout logic [8:1] pmod, - - // Onboard RAM - output logic ram_clk, - inout logic [15:0] ram_data, - output logic [13:0] ram_addr, - output logic [1:0] ram_dqm, - output logic [1:0] ram_bs, - output logic ram_cke, - output logic ram_ras, - output logic ram_cas, - output logic ram_we, - output logic ram_cs -); - -// This is the top module, enter your design here -// Happy HDL :] - -endmodule diff --git a/Max10_VGA/top_tb.sv.bak b/Max10_VGA/top_tb.sv.bak deleted file mode 100644 index 8ec50bd..0000000 --- a/Max10_VGA/top_tb.sv.bak +++ /dev/null @@ -1,24 +0,0 @@ -`timescale 1 ns / 100 ps - -module tb(); - reg clk = 1'b0; - - reg [14:0] v_gpio_d; - reg [8:1] v_led; - - VGA_Controller VGA_Controller_Inst( - .pixel_clk(clk), - .gpio_d(v_gpio_d) - ); - - // 25MHz clock - always #5 clk <= ~clk; - - - initial begin - $display($time, " Starting the Simulation"); - #1000 - $finish(); - end - -endmodule diff --git a/Max10_VGA/vga_controller.sv.bak b/Max10_VGA/vga_controller.sv.bak deleted file mode 100644 index a94004a..0000000 --- a/Max10_VGA/vga_controller.sv.bak +++ /dev/null @@ -1,8 +0,0 @@ -module VGA_Controller( - input wire pixel_clk, - inout logic [14:0] gpio_d, - output logic [8:1] led -}; - - -endmodule diff --git a/Max10_VGA/vga_test_screen.sv.bak b/Max10_VGA/vga_test_screen.sv.bak deleted file mode 100644 index 23864f1..0000000 --- a/Max10_VGA/vga_test_screen.sv.bak +++ /dev/null @@ -1,5 +0,0 @@ -VGA_Test_Screen( - input wire [10:0] scan_pos_x, - input wire [10:0] scan_pos_y, - output wire [2:0] rgb, -); \ No newline at end of file