From 4e96b00f95a95dce8e43ea22c2e7013ba4e87a53 Mon Sep 17 00:00:00 2001
From: Benjamin Kyd <benjaminkyd@gmail.com>
Date: Mon, 6 Jun 2022 20:59:52 +0100
Subject: [PATCH] VGAtiming

---
 Max10_VGA/top.sv             | 35 +++++++++++-----------
 Max10_VGA/vga_controller.sv  | 57 ++++++++++++++++--------------------
 Max10_VGA/vga_test_screen.sv | 32 +++++++++++++++-----
 readme.md                    |  7 +++++
 4 files changed, 73 insertions(+), 58 deletions(-)
 create mode 100644 readme.md

diff --git a/Max10_VGA/top.sv b/Max10_VGA/top.sv
index 78ed605..9829188 100644
--- a/Max10_VGA/top.sv
+++ b/Max10_VGA/top.sv
@@ -4,43 +4,42 @@ module top (
 	// Header GPIO
 	inout  logic [14:0] gpio_d,
 	// Onboard LEDs
-	output logic  [8:1] led
+	output logic [8:1] led
 );
 	wire pixel_clk;
 	
 	PLL p_clk_pll (clk12m, pixel_clk);
 	
-	wire vsync_pulse, hsync_pulse;
-	
-	// 1111111111 = NO DRAW
-	wire [10:0] scan_pos_x;
-	wire [10:0] scan_pos_y;
-	
 	wire [2:0] rgb;
 
+	wire [9:0] hcounter;
+	wire [9:0] vcounter;
+	
+	wire hsync;
+	wire vsync;
+	
 	VGA_Signal_Gen VGA_Signal_Gen_Inst(
 		.pixel_clk(pixel_clk),
-		.scan_x(scan_pos_x),
-		.scan_y(scan_pos_y),
-		.h_sync(hsync_pulse),
-		.v_sync(vsync_pulse)
+		.hcounter(hcounter),
+		.vcounter(vcounter),
+		.hsync(hsync),
+		.vsync(vsync)
 	);
 	
 	VGA_Test_Screen VGA_Test_Screen_Inst(
 		.pixel_clk(pixel_clk),
-		.x(scan_pos_x),
-		.y(scan_pos_y),
+		.x(hcounter),
+		.y(vcounter),
 		.rgb(rgb)
 	);
 	
-	assign gpio_d[14] = hsync_pulse;
-	assign gpio_d[13] = vsync_pulse;
-	
+	assign gpio_d[14] = hsync;
+	assign gpio_d[13] = vsync;
 	assign gpio_d[11:9] = rgb;
-	
+		
 	// OopSS, need a fake ground pin here
 	assign gpio_d[6] = 0;
 
-	assign led[1] = 1;
+	assign led[1] = vsync;
 	
 endmodule
diff --git a/Max10_VGA/vga_controller.sv b/Max10_VGA/vga_controller.sv
index bb3a778..74b6a8d 100644
--- a/Max10_VGA/vga_controller.sv
+++ b/Max10_VGA/vga_controller.sv
@@ -1,41 +1,34 @@
-module VGA_Signal_Gen
- #(parameter TOTAL_COLS  = 800, 
-   parameter TOTAL_ROWS  = 525,
-   parameter ACTIVE_COLS = 640, 
-   parameter ACTIVE_ROWS = 480)(
+module VGA_Signal_Gen(
 	input wire pixel_clk,
-	output wire [10:0] scan_x,
-	output wire [10:0] scan_y,
-	output wire h_sync,
-	output wire v_sync
+	output reg [9:0] hcounter,
+	output reg [9:0] vcounter,
+	output wire hsync,
+	output wire vsync
 );
 	
-	reg [9:0] h_counter;
-	reg [9:0] v_counter;
-	
-	// VGA 640 x 480 @ 60 Hz
-	// pixel_clk 25.175MHz
 	always @(posedge pixel_clk) begin
-		if (h_counter <= 800) begin
-			h_counter <= h_counter + 1;
-		end else begin
-			// reset scanline
-			h_counter <= 1'b0;
+		if(hcounter == 799) begin
 			
-			// step v_counter after hline
-			if (v_counter <= 525) begin
-				v_counter <= v_counter + 1;
-			end else begin
-				v_counter <= 1'b0;
-			end
+		hcounter <= 0;
+			
+		if(vcounter == 524)
+			vcounter <= 0;
+		else 
+			vcounter <= vcounter + 1'b1;
+		 
 		end
+		else
+			hcounter <= hcounter + 1'b1;
+	 
+		if (vcounter >= 490 && vcounter < 492) 
+			vsync <= 1'b0;
+		else
+			vsync <= 1'b1;
+
+		if (hcounter >= 656 && hcounter < 752) 
+			hsync <= 1'b0;
+		else
+			hsync <= 1'b1;
 	end
-	
-	// generate sync pulses
-	assign h_sync = ~(h_counter <= 96);
-	assign v_sync = ~(v_counter <= 2);
-	
-	assign scan_x = h_counter + 48;
-	assign scan_y = v_counter + 33;
 
 endmodule
diff --git a/Max10_VGA/vga_test_screen.sv b/Max10_VGA/vga_test_screen.sv
index c40d846..1539904 100644
--- a/Max10_VGA/vga_test_screen.sv
+++ b/Max10_VGA/vga_test_screen.sv
@@ -1,15 +1,31 @@
 module VGA_Test_Screen(
 	input wire pixel_clk,
-	input wire [10:0] x,
-	input wire [10:0] y,
+	input reg [10:0] x,
+	input reg [10:0] y,
 	output reg [2:0] rgb
 );
 
-
-	always @(posedge pixel_clk) begin
-		if (x > 20) begin
-			rgb[1] <= 1;
-		end
-	end
+	always @ (posedge pixel_clk) begin
+	
+		 if (x < 80 && y < 480)
+			rgb <= 3'b111;
+		 else if (x < 160 && y < 480)
+			rgb <= 3'b110;
+		 else if (x < 240 && y < 480)
+			rgb <= 3'b101;
+		 else if (x < 320 && y < 480)
+			rgb <= 3'b100;
+		 else if (x < 400 && y < 480)
+			rgb <= 3'b011;
+		 else if (x < 480 && y < 480)
+			rgb <= 3'b010;
+		 else if (x < 560 && y < 480)
+		 	rgb <= 3'b001;
+		 else if (x < 640 && y < 480)
+			rgb <= 3'b000;
+		 else 
+			rgb <= 3'b000;
+			
+	end 
 	
 endmodule
diff --git a/readme.md b/readme.md
new file mode 100644
index 0000000..83c2d5c
--- /dev/null
+++ b/readme.md
@@ -0,0 +1,7 @@
+# FPGA Basics
+
+A Collection of simple FPGA Projects to learn the basics of FPGA programming.
+
+| Dev Board | FPGA | Project | Description |
+| -- | -- | -- | -- |
+| [Max 1000](https://vhdplus.com/docs/components/max1000/) | MAX10M08 | [VGA Driver](/Max10_VGA/) | VGA Driver |
\ No newline at end of file