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\ No newline at end of file diff --git a/Verilator_Tests/spi/spi_master.v b/Verilator_Tests/spi/spi_master.v new file mode 100644 index 0000000..6da8b00 --- /dev/null +++ b/Verilator_Tests/spi/spi_master.v @@ -0,0 +1,81 @@ +module spi_master ( + input wire clk, + + output reg spi_clk = 0, + + input wire start, // Pulse high to begin transfer + input reg [7:0] data_out = 8'd0, + output reg spi_mosi = 0, + + output wire [7:0] data_in, + input wire spi_miso, + + output reg busy = 0, + output reg spi_cs = 1 // Active low +); +// SPI Mode 0: CPOL = 0, CPHA = 0 (drive on falling, sample on rising) +reg [3:0] bit_cnt = 0; +reg [7:0] shift_reg_in = 0; +reg [7:0] shift_reg_out = 0; + +typedef enum logic [1:0] { + IDLE, + CHIP_SEL, + BUSY, + DONE +} state_t; + +state_t state = IDLE; + +always @(posedge clk) begin + case (state) + IDLE: begin + spi_cs <= 1; + spi_clk <= 0; + busy <= 0; + + if (start) begin + state <= CHIP_SEL; + shift_reg_out <= data_out; + bit_cnt <= 0; + end + end + + // data is one cycle after CS is brought low + CHIP_SEL: begin + spi_cs <= 0; + busy <= 1; + state <= BUSY; + end + + BUSY: begin + if (clk) begin + spi_clk <= ~spi_clk; + + // Falling, drive data + if (!spi_clk) begin + spi_mosi <= shift_reg_out[7]; + shift_reg_out <= {shift_reg_out[6:0], 1'b0}; + + end else begin + // Rising, sample data + shift_reg_in <= {shift_reg_in[6:0], spi_miso}; + bit_cnt <= bit_cnt + 1; + + if (bit_cnt == 7) begin + state <= DONE; + end + end + end + end + + DONE: begin + spi_cs <= 1; + data_in <= {shift_reg_in[6:0], spi_miso}; + state <= IDLE; + end + endcase +end + +endmodule + diff --git a/Verilator_Tests/spi/top.v b/Verilator_Tests/spi/top.v index c77e3da..89a1e0c 100644 --- a/Verilator_Tests/spi/top.v +++ b/Verilator_Tests/spi/top.v @@ -1,62 +1,36 @@ module top ( - input wire clk_25mhz, + input wire clk_25mhz, output wire spi_clk, output wire spi_mosi, - input wire spi_miso, + input wire spi_miso, output wire spi_cs ); -reg[7:0] miso; -reg[7:0] mosi = 8'b01101011; +// we would prefer fifo +wire[7:0] miso; +wire[7:0] mosi = 8'b01101011; + +reg busy = 0; +reg start = 0; + +always @(posedge clk_25mhz) begin + start <= 0; + if (!busy && !start) begin + start <= 1; + end +end spi_master spimaster0( - .clk_25mhz(clk_25mhz), + .clk(clk_25mhz), .spi_clk(spi_clk), - .data_in(mosi), - .spi_miso(spi_miso), + .start(start), .data_out(mosi), .spi_mosi(spi_mosi), + .data_in(miso), + .spi_miso(spi_miso), + .busy(busy), .spi_cs(spi_cs) ); endmodule - - -module spi_master ( - input wire clk_25mhz, - - output reg spi_clk = 0, - - output reg[7:0] data_in, - output reg spi_miso = 0, - - input reg[7:0] data_out, - input reg spi_mosi = 0, - - output wire spi_cs -); - - -assign spi_cs = 0; // Always selected (for test) - -reg [7:0] mosi_shift = 8'b01101011; // Example byte -reg [3:0] bit_counter = 0; -reg spi_clk_en = 1; - -localparam TRANSFERRING = 0, IDLE = 1; -wire spi_state = IDLE; - -always_ff @(posedge clk_25mhz) begin - spi_clk <= ~spi_clk; - - if (spi_clk == 0) begin - // Falling edge: shift data - spi_mosi <= mosi_shift[7]; - mosi_shift <= {mosi_shift[6:0], 1'b0}; - bit_counter <= bit_counter + 1; - end -end - -endmodule - diff --git a/Verilator_Tests/spi/wave.vcd b/Verilator_Tests/spi/wave.vcd index 5e2aad0..554a5b9 100644 --- a/Verilator_Tests/spi/wave.vcd +++ b/Verilator_Tests/spi/wave.vcd @@ -1,730 +1,858 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end $scope module TOP $end - $var wire 1 # clk_25mhz $end - $var wire 1 $ spi_clk $end - $var wire 1 % spi_mosi $end - $var wire 1 & spi_miso $end - $var wire 1 ' spi_cs $end + $var wire 1 * clk_25mhz $end + $var wire 1 + spi_clk $end + $var wire 1 , spi_mosi $end + $var wire 1 - spi_miso $end + $var wire 1 . spi_cs $end $scope module top $end - $var wire 1 # clk_25mhz $end - $var wire 1 $ spi_clk $end - $var wire 1 % spi_mosi $end - $var wire 1 & spi_miso $end - $var wire 1 ' spi_cs $end - $var wire 8 ( mosi_shift [7:0] $end - $var wire 4 ) bit_counter [3:0] $end - $var wire 1 * spi_clk_en $end + $var wire 1 * clk_25mhz $end + $var wire 1 + spi_clk $end + $var wire 1 , spi_mosi $end + $var wire 1 - spi_miso $end + $var wire 1 . spi_cs $end + $var wire 8 # miso [7:0] $end + $var wire 8 / mosi [7:0] $end + $var wire 1 $ busy $end + $var wire 1 % start $end + $scope module spimaster0 $end + $var wire 1 * clk $end + $var wire 1 + spi_clk $end + $var wire 1 % start $end + $var wire 8 / data_out [7:0] $end + $var wire 1 , spi_mosi $end + $var wire 8 # data_in [7:0] $end + $var wire 1 - spi_miso $end + $var wire 1 $ busy $end + $var wire 1 . spi_cs $end + $var wire 4 & bit_cnt [3:0] $end + $var wire 8 ' shift_reg_in [7:0] $end + $var wire 8 ( shift_reg_out [7:0] $end + $var wire 2 ) state [1:0] $end + $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 -1# +b00000000 # 0$ 0% -0& -0' -b01101011 ( -b0000 ) -0* -#20 -0# -#40 -1# -1$ -b11010110 ( -b0001 ) -#60 -0# -#80 -1# -0$ -#100 -0# -#120 -1# -1$ -1% -b10101100 ( -b0010 ) -#140 -0# -#160 -1# -0$ -#180 -0# -#200 -1# -1$ -b01011000 ( -b0011 ) -#220 -0# -#240 -1# -0$ -#260 -0# -#280 -1# -1$ -0% -b10110000 ( -b0100 ) -#300 -0# -#320 -1# -0$ -#340 -0# -#360 -1# -1$ -1% -b01100000 ( -b0101 ) -#380 -0# -#400 -1# -0$ -#420 -0# -#440 -1# -1$ -0% -b11000000 ( -b0110 ) -#460 -0# -#480 -1# -0$ -#500 -0# -#520 -1# -1$ -1% -b10000000 ( -b0111 ) -#540 -0# -#560 -1# -0$ -#580 -0# -#600 -1# -1$ +b0000 & +b00000000 ' b00000000 ( -b1000 ) -#620 -0# -#640 -1# -0$ -#660 -0# -#680 -1# -1$ +b00 ) +1* +0+ +0, +0- +1. +b01101011 / +#20 +0* +#40 +1% +1* +#60 +0* +#80 0% -b1001 ) +b01101011 ( +b01 ) +1* +#100 +0* +#120 +1$ +1% +b10 ) +1* +0. +#140 +0* +#160 +0% +b11010110 ( +1* +1+ +#180 +0* +#200 +b0001 & +1* +0+ +#220 +0* +#240 +b10101100 ( +1* +1+ +1, +#260 +0* +#280 +b0010 & +1* +0+ +#300 +0* +#320 +b01011000 ( +1* +1+ +#340 +0* +#360 +b0011 & +1* +0+ +#380 +0* +#400 +b10110000 ( +1* +1+ +0, +#420 +0* +#440 +b0100 & +1* +0+ +#460 +0* +#480 +b01100000 ( +1* +1+ +1, +#500 +0* +#520 +b0101 & +1* +0+ +#540 +0* +#560 +b11000000 ( +1* +1+ +0, +#580 +0* +#600 +b0110 & +1* +0+ +#620 +0* +#640 +b10000000 ( +1* +1+ +1, +#660 +0* +#680 +b0111 & +1* +0+ #700 -0# +0* #720 -1# -0$ +b00000000 ( +1* +1+ #740 -0# +0* #760 -1# -1$ -b1010 ) +b1000 & +b11 ) +1* +0+ #780 -0# +0* #800 -1# -0$ +b00 ) +1* +1. #820 -0# +0* #840 -1# -1$ -b1011 ) +0$ +1* #860 -0# +0* #880 -1# -0$ +1% +1* #900 -0# +0* #920 -1# -1$ -b1100 ) +0% +b0000 & +b01101011 ( +b01 ) +1* #940 -0# +0* #960 -1# -0$ +1$ +1% +b10 ) +1* +0. #980 -0# +0* #1000 -1# -1$ -b1101 ) +0% +b11010110 ( +1* +1+ +0, #1020 -0# +0* #1040 -1# -0$ +b0001 & +1* +0+ #1060 -0# +0* #1080 -1# -1$ -b1110 ) +b10101100 ( +1* +1+ +1, #1100 -0# +0* #1120 -1# -0$ +b0010 & +1* +0+ #1140 -0# +0* #1160 -1# -1$ -b1111 ) +b01011000 ( +1* +1+ #1180 -0# +0* #1200 -1# -0$ +b0011 & +1* +0+ #1220 -0# +0* #1240 -1# -1$ -b0000 ) +b10110000 ( +1* +1+ +0, #1260 -0# +0* #1280 -1# -0$ +b0100 & +1* +0+ #1300 -0# +0* #1320 -1# -1$ -b0001 ) +b01100000 ( +1* +1+ +1, #1340 -0# +0* #1360 -1# -0$ +b0101 & +1* +0+ #1380 -0# +0* #1400 -1# -1$ -b0010 ) +b11000000 ( +1* +1+ +0, #1420 -0# +0* #1440 -1# -0$ +b0110 & +1* +0+ #1460 -0# +0* #1480 -1# -1$ -b0011 ) +b10000000 ( +1* +1+ +1, #1500 -0# +0* #1520 -1# -0$ +b0111 & +1* +0+ #1540 -0# +0* #1560 -1# -1$ -b0100 ) +b00000000 ( +1* +1+ #1580 -0# +0* #1600 -1# -0$ +b1000 & +b11 ) +1* +0+ #1620 -0# +0* #1640 -1# -1$ -b0101 ) +b00 ) +1* +1. #1660 -0# +0* #1680 -1# 0$ +1* #1700 -0# +0* #1720 -1# -1$ -b0110 ) +1% +1* #1740 -0# +0* #1760 -1# -0$ +0% +b0000 & +b01101011 ( +b01 ) +1* #1780 -0# +0* #1800 -1# 1$ -b0111 ) +1% +b10 ) +1* +0. #1820 -0# +0* #1840 -1# -0$ +0% +b11010110 ( +1* +1+ +0, #1860 -0# +0* #1880 -1# -1$ -b1000 ) +b0001 & +1* +0+ #1900 -0# +0* #1920 -1# -0$ +b10101100 ( +1* +1+ +1, #1940 -0# +0* #1960 -1# -1$ -b1001 ) +b0010 & +1* +0+ #1980 -0# +0* #2000 -1# -0$ +b01011000 ( +1* +1+ #2020 -0# +0* #2040 -1# -1$ -b1010 ) +b0011 & +1* +0+ #2060 -0# +0* #2080 -1# -0$ +b10110000 ( +1* +1+ +0, #2100 -0# +0* #2120 -1# -1$ -b1011 ) +b0100 & +1* +0+ #2140 -0# +0* #2160 -1# -0$ +b01100000 ( +1* +1+ +1, #2180 -0# +0* #2200 -1# -1$ -b1100 ) +b0101 & +1* +0+ #2220 -0# +0* #2240 -1# -0$ +b11000000 ( +1* +1+ +0, #2260 -0# +0* #2280 -1# -1$ -b1101 ) +b0110 & +1* +0+ #2300 -0# +0* #2320 -1# -0$ +b10000000 ( +1* +1+ +1, #2340 -0# +0* #2360 -1# -1$ -b1110 ) +b0111 & +1* +0+ #2380 -0# +0* #2400 -1# -0$ +b00000000 ( +1* +1+ #2420 -0# +0* #2440 -1# -1$ -b1111 ) +b1000 & +b11 ) +1* +0+ #2460 -0# +0* #2480 -1# -0$ +b00 ) +1* +1. #2500 -0# +0* #2520 -1# -1$ -b0000 ) +0$ +1* #2540 -0# +0* #2560 -1# -0$ +1% +1* #2580 -0# +0* #2600 -1# -1$ -b0001 ) +0% +b0000 & +b01101011 ( +b01 ) +1* #2620 -0# +0* #2640 -1# -0$ +1$ +1% +b10 ) +1* +0. #2660 -0# +0* #2680 -1# -1$ -b0010 ) +0% +b11010110 ( +1* +1+ +0, #2700 -0# +0* #2720 -1# -0$ +b0001 & +1* +0+ #2740 -0# +0* #2760 -1# -1$ -b0011 ) +b10101100 ( +1* +1+ +1, #2780 -0# +0* #2800 -1# -0$ +b0010 & +1* +0+ #2820 -0# +0* #2840 -1# -1$ -b0100 ) +b01011000 ( +1* +1+ #2860 -0# +0* #2880 -1# -0$ +b0011 & +1* +0+ #2900 -0# +0* #2920 -1# -1$ -b0101 ) +b10110000 ( +1* +1+ +0, #2940 -0# +0* #2960 -1# -0$ +b0100 & +1* +0+ #2980 -0# +0* #3000 -1# -1$ -b0110 ) +b01100000 ( +1* +1+ +1, #3020 -0# +0* #3040 -1# -0$ +b0101 & +1* +0+ #3060 -0# +0* #3080 -1# -1$ -b0111 ) +b11000000 ( +1* +1+ +0, #3100 -0# +0* #3120 -1# -0$ +b0110 & +1* +0+ #3140 -0# +0* #3160 -1# -1$ -b1000 ) +b10000000 ( +1* +1+ +1, #3180 -0# +0* #3200 -1# -0$ +b0111 & +1* +0+ #3220 -0# +0* #3240 -1# -1$ -b1001 ) +b00000000 ( +1* +1+ #3260 -0# +0* #3280 -1# -0$ +b1000 & +b11 ) +1* +0+ #3300 -0# +0* #3320 -1# -1$ -b1010 ) +b00 ) +1* +1. #3340 -0# +0* #3360 -1# 0$ +1* #3380 -0# +0* #3400 -1# -1$ -b1011 ) +1% +1* #3420 -0# +0* #3440 -1# -0$ +0% +b0000 & +b01101011 ( +b01 ) +1* #3460 -0# +0* #3480 -1# 1$ -b1100 ) +1% +b10 ) +1* +0. #3500 -0# +0* #3520 -1# -0$ +0% +b11010110 ( +1* +1+ +0, #3540 -0# +0* #3560 -1# -1$ -b1101 ) +b0001 & +1* +0+ #3580 -0# +0* #3600 -1# -0$ +b10101100 ( +1* +1+ +1, #3620 -0# +0* #3640 -1# -1$ -b1110 ) +b0010 & +1* +0+ #3660 -0# +0* #3680 -1# -0$ +b01011000 ( +1* +1+ #3700 -0# +0* #3720 -1# -1$ -b1111 ) +b0011 & +1* +0+ #3740 -0# +0* #3760 -1# -0$ +b10110000 ( +1* +1+ +0, #3780 -0# +0* #3800 -1# -1$ -b0000 ) +b0100 & +1* +0+ #3820 -0# +0* #3840 -1# -0$ +b01100000 ( +1* +1+ +1, #3860 -0# +0* #3880 -1# -1$ -b0001 ) +b0101 & +1* +0+ #3900 -0# +0* #3920 -1# -0$ +b11000000 ( +1* +1+ +0, #3940 -0# +0* #3960 -1# -1$ -b0010 ) +b0110 & +1* +0+ #3980 -0# +0* #4000 -1# -0$ +b10000000 ( +1* +1+ +1, #4020 -0# +0* #4040 -1# -1$ -b0011 ) +b0111 & +1* +0+ #4060 -0# +0* #4080 -1# -0$ +b00000000 ( +1* +1+ #4100 -0# +0* #4120 -1# -1$ -b0100 ) +b1000 & +b11 ) +1* +0+ #4140 -0# +0* #4160 -1# -0$ +b00 ) +1* +1. #4180 -0# +0* #4200 -1# -1$ -b0101 ) +0$ +1* #4220 -0# +0* #4240 -1# -0$ +1% +1* #4260 -0# +0* #4280 -1# -1$ -b0110 ) +0% +b0000 & +b01101011 ( +b01 ) +1* #4300 -0# +0* #4320 -1# -0$ +1$ +1% +b10 ) +1* +0. #4340 -0# +0* #4360 -1# -1$ -b0111 ) +0% +b11010110 ( +1* +1+ +0, #4380 -0# +0* #4400 -1# -0$ +b0001 & +1* +0+ #4420 -0# +0* #4440 -1# -1$ -b1000 ) +b10101100 ( +1* +1+ +1, #4460 -0# +0* #4480 -1# -0$ +b0010 & +1* +0+ #4500 -0# +0* #4520 -1# -1$ -b1001 ) +b01011000 ( +1* +1+ #4540 -0# +0* #4560 -1# -0$ +b0011 & +1* +0+ #4580 -0# +0* #4600 -1# -1$ -b1010 ) +b10110000 ( +1* +1+ +0, #4620 -0# +0* #4640 -1# -0$ +b0100 & +1* +0+ #4660 -0# +0* #4680 -1# -1$ -b1011 ) +b01100000 ( +1* +1+ +1, #4700 -0# +0* #4720 -1# -0$ +b0101 & +1* +0+ #4740 -0# +0* #4760 -1# -1$ -b1100 ) +b11000000 ( +1* +1+ +0, #4780 -0# +0* #4800 -1# -0$ +b0110 & +1* +0+ #4820 -0# +0* #4840 -1# -1$ -b1101 ) +b10000000 ( +1* +1+ +1, #4860 -0# +0* #4880 -1# -0$ +b0111 & +1* +0+ #4900 -0# +0* #4920 -1# -1$ -b1110 ) +b00000000 ( +1* +1+ #4940 -0# +0* #4960 -1# -0$ +b1000 & +b11 ) +1* +0+ #4980 -0# +0* #4999