diff --git a/.gitignore b/.gitignore
index 0ae8b25..0952f75 100644
--- a/.gitignore
+++ b/.gitignore
@@ -4,5 +4,6 @@ build/
 bin/
 .obj_dir/
 obj_dir/
-.nvim/
+*.nvim/
 .cache/
+*.vcd/
diff --git a/.nvim/svlangserver/index.json b/.nvim/svlangserver/index.json
index f0856df..b4cc621 100644
--- a/.nvim/svlangserver/index.json
+++ b/.nvim/svlangserver/index.json
@@ -1 +1 @@
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\ No newline at end of file
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],[],["instance","PLL"]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_VGA/PLL.v",[[[[[["PLL",[[39,0],[41,5]],[[39,7],[39,10]],[],["module"]],[149,0]],[[["inclk0",[[43,9],[43,15]],[[43,9],[43,15]],["PLL"],["port"]],["c0",[[41,1],[41,3]],[[41,1],[41,3]],["PLL"],["port","inclk0"]],["c0",[[44,10],[44,12]],[[44,10],[44,12]],["PLL"],["port"]],["sub_wire2",[[46,1],[46,28]],[[46,12],[46,21]],["PLL"],["variable","wire"]],["sub_wire3",[[47,1],[47,21]],[[47,12],[47,21]],["PLL"],["variable","wire"]],["sub_wire0",[[48,1],[48,25]],[[48,7],[48,16]],["PLL"],["variable","wire"]],["sub_wire1",[[49,1],[49,46]],[[49,12],[49,21]],["PLL"],["variable","wire"]],["sub_wire4",[[50,1],[50,38]],[[50,12],[50,21]],["PLL"],["variable","wire"]],["c0",[[51,1],[51,21]],[[51,7],[51,9]],["PLL"],["variable","wire"]],["altpll_component",[[53,1],[90,22]],[[53,8],[53,24]],["PLL"],["instance","altpll"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_VGA/top_tb.sv",[[[[[["tb",[[2,0],[2,12]],[[2,7],[2,9]],[],["module"]],[37,9]],[[["clk",[[3,1],[3,15]],[[3,5],[3,8]],["tb"],["variable","reg"]],["v_h_sync",[[5,1],[5,14]],[[5,6],[5,14]],["tb"],["variable","wire"]],["v_v_sync",[[6,1],[6,14]],[[6,6],[6,14]],["tb"],["variable","wire"]],["scan_pos_x",[[8,1],[8,23]],[[8,13],[8,23]],["tb"],["variable","wire"]],["scan_pos_y",[[9,1],[9,23]],[[9,13],[9,23]],["tb"],["variable","wire"]],["rgb",[[11,1],[11,15]],[[11,12],[11,15]],["tb"],["variable","wire"]],["VGA_Test_Screen_Inst",[[13,1],[18,2]],[[13,17],[13,37]],["tb"],["instance","VGA_Test_Screen"]],["VGA_Signal_Gen_Inst",[[20,1],[26,2]],[[20,16],[20,35]],["tb"],["instance","VGA_Signal_Gen"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_VGA/top.sv",[[[[[["top",[[0,0],[7,2]],[[0,7],[0,10]],[],["module"]],[44,9]],[[["clk12m",[[2,1],[2,19]],[[2,13],[2,19]],["top"],["port","logic"]],["gpio_d",[[4,1],[4,27]],[[4,21],[4,27]],["top"],["port","logic"]],["led",[[6,1],[6,23]],[[6,20],[6,23]],["top"],["port","logic"]],["pixel_clk",[[8,1],[8,15]],[[8,6],[8,15]],["top"],["variable","wire"]],["p_clk_pll",[[10,1],[10,34]],[[10,5],[10,14]],["top"],["instance","PLL"]],["rgb",[[12,1],[12,15]],[[12,12],[12,15]],["top"],["variable","wire"]],["hcounter",[[14,1],[14,20]],[[14,12],[14,20]],["top"],["variable","wire"]],["vcounter",[[15,1],[15,20]],[[15,12],[15,20]],["top"],["variable","wire"]],["hsync",[[17,1],[17,11]],[[17,6],[17,11]],["top"],["variable","wire"]],["vsync",[[18,1],[18,11]],[[18,6],[18,11]],["top"],["variable","wire"]],["VGA_Signal_Gen_Inst",[[20,1],[26,2]],[[20,16],[20,35]],["top"],["instance","VGA_Signal_Gen"]],["VGA_Test_Screen_Inst",[[28,1],[33,2]],[[28,17],[28,37]],["top"],["instance","VGA_Test_Screen"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_VGA/vga_controller.sv",[[[[[["VGA_Signal_Gen",[[0,0],[6,2]],[[0,7],[0,21]],[],["module"]],[33,9]],[[["pixel_clk",[[1,1],[1,21]],[[1,12],[1,21]],["VGA_Signal_Gen"],["port","wire"]],["hcounter",[[2,1],[2,26]],[[2,18],[2,26]],["VGA_Signal_Gen"],["port","reg"]],["vcounter",[[3,1],[3,26]],[[3,18],[3,26]],["VGA_Signal_Gen"],["port","reg"]],["hsync",[[4,1],[4,18]],[[4,13],[4,18]],["VGA_Signal_Gen"],["port","wire"]],["vsync",[[5,1],[5,18]],[[5,13],[5,18]],["VGA_Signal_Gen"],["port","wire"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_VGA/vga_test_screen.sv",[[[[[["VGA_Test_Screen",[[0,0],[5,2]],[[0,7],[0,22]],[],["module"]],[30,9]],[[["pixel_clk",[[1,1],[1,21]],[[1,12],[1,21]],["VGA_Test_Screen"],["port","wire"]],["x",[[2,1],[2,19]],[[2,18],[2,19]],["VGA_Test_Screen"],["port","reg"]],["y",[[3,1],[3,19]],[[3,18],[3,19]],["VGA_Test_Screen"],["port","reg"]],["rgb",[[4,1],[4,21]],[[4,18],[4,21]],["VGA_Test_Screen"],["port","reg"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max1000 Template/top.sv",[[[[[["max1000_template",[[0,0],[36,2]],[[0,7],[0,23]],[],["module"]],[41,9]],[[["clk12m",[[2,1],[2,19]],[[2,13],[2,19]],["max1000_template"],["port","logic"]],["acc_sclk",[[5,1],[5,22]],[[5,14],[5,22]],["max1000_template"],["port","logic"]],["acc_mosi",[[6,1],[6,22]],[[6,14],[6,22]],["max1000_template"],["port","logic"]],["acc_miso",[[7,1],[7,22]],[[7,14],[7,22]],["max1000_template"],["port","logic"]],["acc_cs",[[8,1],[8,20]],[[8,14],[8,20]],["max1000_template"],["port","logic"]],["acc_int1",[[9,1],[9,22]],[[9,14],[9,22]],["max1000_template"],["port","logic"]],["acc_int2",[[10,1],[10,22]],[[10,14],[10,22]],["max1000_template"],["port","logic"]],["btn",[[13,1],[13,17]],[[13,14],[13,17]],["max1000_template"],["port","logic"]],["gpio_d",[[16,1],[16,27]],[[16,21],[16,27]],["max1000_template"],["port","logic"]],["gpio_a",[[17,1],[17,27]],[[17,21],[17,27]],["max1000_template"],["port","logic"]],["led",[[20,1],[20,24]],[[20,21],[20,24]],["max1000_template"],["port","logic"]],["pmod",[[23,1],[23,25]],[[23,21],[23,25]],["max1000_template"],["port","logic"]],["ram_clk",[[26,1],[26,28]],[[26,21],[26,28]],["max1000_template"],["port","logic"]],["ram_data",[[27,1],[27,29]],[[27,21],[27,29]],["max1000_template"],["port","logic"]],["ram_addr",[[28,1],[28,29]],[[28,21],[28,29]],["max1000_template"],["port","logic"]],["ram_dqm",[[29,1],[29,28]],[[29,21],[29,28]],["max1000_template"],["port","logic"]],["ram_bs",[[30,1],[30,27]],[[30,21],[30,27]],["max1000_template"],["port","logic"]],["ram_cke",[[31,1],[31,28]],[[31,21],[31,28]],["max1000_template"],["port","logic"]],["ram_ras",[[32,1],[32,28]],[[32,21],[32,28]],["max1000_template"],["port","logic"]],["ram_cas",[[33,1],[33,28]],[[33,21],[33,28]],["max1000_template"],["port","logic"]],["ram_we",[[34,1],[34,27]],[[34,21],[34,27]],["max1000_template"],["port","logic"]],["ram_cs",[[35,1],[35,27]],[[35,21],[35,27]],["max1000_template"],["port","logic"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Verilator_Tests/clk/top_tb.v",[[[[[["top_tb",[[4,0],[4,14]],[[4,7],[4,13]],[],["module"]],[21,9]],[[["clk_25mhz",[[6,4],[6,21]],[[6,8],[6,17]],["top_tb"],["variable","reg"]],["uut",[[8,4],[10,5]],[[8,8],[8,11]],["top_tb"],["instance","top"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Verilator_Tests/clk/top.v",[[[[[["top",[[0,0],[2,2]],[[0,7],[0,10]],[],["module"]],[4,9]],[[["clk_25mhz",[[1,4],[1,19]],[[1,10],[1,19]],["top"],["port","input"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Verilator_Tests/spi/top_tb.v",[[[[[["top_tb",[[4,0],[4,14]],[[4,7],[4,13]],[],["module"]],[26,9]],[[["clk_25mhz",[[6,4],[6,21]],[[6,8],[6,17]],["top_tb"],["variable","reg"]],["spi_clk",[[7,4],[7,15]],[[7,8],[7,15]],["top_tb"],["variable","reg"]],["spi_mosi",[[7,4],[7,25]],[[7,17],[7,25]],["top_tb"],["variable","spi_clk"]],["spi_miso",[[7,4],[7,35]],[[7,27],[7,35]],["top_tb"],["variable","spi_mosi"]],["spi_cs",[[7,4],[7,43]],[[7,37],[7,43]],["top_tb"],["variable","spi_miso"]],["uut",[[9,4],[15,5]],[[9,8],[9,11]],["top_tb"],["instance","top"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Verilator_Tests/spi/top.v",[[[[[["top",[[0,0],[9,2]],[[0,7],[0,10]],[],["module"]],[28,9]],[[["clk_25mhz",[[1,4],[1,24]],[[1,15],[1,24]],["top"],["port","wire"]],["spi_clk",[[3,4],[3,26]],[[3,15],[3,22]],["top"],["port","reg"]],["spi_mosi",[[5,4],[5,27]],[[5,15],[5,23]],["top"],["port","reg"]],["spi_miso",[[6,4],[6,26]],[[6,14],[6,22]],["top"],["port","reg"]],["spi_cs",[[8,4],[8,22]],[[8,16],[8,22]],["top"],["port","wire"]],["mosi_shift",[[13,0],[13,34]],[[13,10],[13,20]],["top"],["variable","reg"]],["bit_counter",[[14,0],[14,25]],[[14,10],[14,21]],["top"],["variable","reg"]],["spi_clk_en",[[15,0],[15,18]],[[15,4],[15,14]],["top"],["variable","reg"]]]]]]],null,0]]]}
\ No newline at end of file
diff --git a/.nvim/svlangserver/linter.vc b/.nvim/svlangserver/linter.vc
index 26b7557..43c7316 100644
--- a/.nvim/svlangserver/linter.vc
+++ b/.nvim/svlangserver/linter.vc
@@ -2,7 +2,9 @@
 +incdir+/home/benk/projects/fpga-basics/Max10_VGA
 +incdir+/home/benk/projects/fpga-basics/Max1000 Template
 +incdir+/home/benk/projects/fpga-basics/Verilator_Tests/clk
++incdir+/home/benk/projects/fpga-basics/Verilator_Tests/spi
 +incdir+/home/benk/projects/fpga-basics/Max10_RT
 +incdir+/home/benk/projects/fpga-basics/Max10_VGA
 +incdir+/home/benk/projects/fpga-basics/Max1000 Template
-+incdir+/home/benk/projects/fpga-basics/Verilator_Tests/clk
\ No newline at end of file
++incdir+/home/benk/projects/fpga-basics/Verilator_Tests/clk
++incdir+/home/benk/projects/fpga-basics/Verilator_Tests/spi
\ No newline at end of file
diff --git a/Verilator_Tests/clk/top.v b/Verilator_Tests/clk/top.v
index 32552dc..db07120 100644
--- a/Verilator_Tests/clk/top.v
+++ b/Verilator_Tests/clk/top.v
@@ -1,15 +1,5 @@
 module top (
-    input clk_25mhz,
-
-    output h_sync,
-    output v_sync,
-
-
-    output [3:0] r,
-    output [3:0] g,
-    output [3:0] b
+    input clk_25mhz
 );
 
-    
-
 endmodule
diff --git a/Verilator_Tests/clk/top_tb.v b/Verilator_Tests/clk/top_tb.v
index 2d38d46..55092ac 100644
--- a/Verilator_Tests/clk/top_tb.v
+++ b/Verilator_Tests/clk/top_tb.v
@@ -6,19 +6,8 @@ module top_tb;
 
     reg clk_25mhz = 0;
 
-    wire h_sync, v_sync;
-
-    wire [3:0] r;
-    wire [3:0] g;
-    wire [3:0] b;
-
     top uut (
         .clk_25mhz(clk_25mhz),
-        .h_sync(h_sync),
-        .v_sync(v_sync),
-        .r(r),
-        .g(g),
-        .b(b)
     );
 
     always #20 clk_25mhz = ~clk_25mhz;
diff --git a/Verilator_Tests/clk/wave.vcd b/Verilator_Tests/clk/wave.vcd
index e828ac4..aa5a91e 100644
--- a/Verilator_Tests/clk/wave.vcd
+++ b/Verilator_Tests/clk/wave.vcd
@@ -2,18 +2,8 @@ $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module TOP $end
   $var wire 1 # clk_25mhz $end
-  $var wire 1 $ h_sync $end
-  $var wire 1 % v_sync $end
-  $var wire 4 & r [3:0] $end
-  $var wire 4 ' g [3:0] $end
-  $var wire 4 ( b [3:0] $end
   $scope module top $end
    $var wire 1 # clk_25mhz $end
-   $var wire 1 $ h_sync $end
-   $var wire 1 % v_sync $end
-   $var wire 4 & r [3:0] $end
-   $var wire 4 ' g [3:0] $end
-   $var wire 4 ( b [3:0] $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
@@ -21,11 +11,6 @@ $enddefinitions $end
 
 #0
 1#
-0$
-0%
-b0000 &
-b0000 '
-b0000 (
 #20
 0#
 #40
diff --git a/Verilator_Tests/spi/Makefile b/Verilator_Tests/spi/Makefile
new file mode 100644
index 0000000..169f930
--- /dev/null
+++ b/Verilator_Tests/spi/Makefile
@@ -0,0 +1,4 @@
+VERILOG = top.v
+DEVICE = um-45k
+
+include ./ulx4m.mk
diff --git a/Verilator_Tests/spi/sim_main.cpp b/Verilator_Tests/spi/sim_main.cpp
new file mode 100644
index 0000000..7a90ee6
--- /dev/null
+++ b/Verilator_Tests/spi/sim_main.cpp
@@ -0,0 +1,29 @@
+#include "Vtop.h"
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+
+int main(int argc, char** argv) {
+    Verilated::commandArgs(argc, argv);
+    Verilated::traceEverOn(true);
+
+    Vtop* top = new Vtop;
+
+    VerilatedVcdC* tfp = new VerilatedVcdC;
+    top->trace(tfp, 99);
+    tfp->open("wave.vcd");
+
+    int clk = 0;
+    for (int time = 0; time < 5000; time++) {
+        // Toggle clk every 20 time units (simulate 25 MHz)
+        if ((time % 20) == 0)
+            clk = !clk;
+
+        top->clk_25mhz = clk;
+        top->eval();
+        tfp->dump(time);
+    }
+
+    tfp->close();
+    delete top;
+    return 0;
+}
diff --git a/Verilator_Tests/spi/top.v b/Verilator_Tests/spi/top.v
new file mode 100644
index 0000000..7ebf62d
--- /dev/null
+++ b/Verilator_Tests/spi/top.v
@@ -0,0 +1,29 @@
+module top (
+    input wire clk_25mhz,
+
+    output reg spi_clk = 0,
+
+    output reg spi_mosi = 0,
+    input reg spi_miso = 0,
+
+    output wire spi_cs
+);
+
+assign spi_cs = 0;  // Always selected (for test)
+
+reg [7:0] mosi_shift = 8'b01101011;  // Example byte
+reg [3:0] bit_counter = 0;
+reg spi_clk_en = 0;
+
+always_ff @(posedge clk_25mhz) begin
+    spi_clk <= ~spi_clk;
+
+    if (spi_clk == 0) begin
+        // Falling edge: shift data
+        spi_mosi <= mosi_shift[7];
+        mosi_shift <= {mosi_shift[6:0], 1'b0};
+        bit_counter <= bit_counter + 1;
+    end
+end
+
+endmodule
diff --git a/Verilator_Tests/spi/top_tb.v b/Verilator_Tests/spi/top_tb.v
new file mode 100644
index 0000000..c24e8a5
--- /dev/null
+++ b/Verilator_Tests/spi/top_tb.v
@@ -0,0 +1,27 @@
+// Copyright 2025 Benjamin Kyd, All Rights Reserved
+
+`timescale 1ns / 1ps
+
+module top_tb;
+
+    reg clk_25mhz = 0;
+    reg spi_clk, spi_mosi, spi_miso, spi_cs;
+
+    top uut (
+        .clk_25mhz(clk_25mhz),
+        .spi_clk(spi_clk),
+        .spi_mosi(spi_mosi),
+        .spi_miso(spi_miso),
+        .spi_cs(spi_cs)
+    );
+
+    always #20 clk_25mhz = ~clk_25mhz;
+
+    initial begin
+        $dumpfile("top_tb.vcd");
+        $dumpvars(0, top_tb);
+
+        #500 $finish;
+    end
+
+endmodule
diff --git a/Verilator_Tests/spi/ulx4m.mk b/Verilator_Tests/spi/ulx4m.mk
new file mode 100644
index 0000000..966b943
--- /dev/null
+++ b/Verilator_Tests/spi/ulx4m.mk
@@ -0,0 +1,47 @@
+PIN_DEF ?= ./ulx4m_v002.lpf
+DEVICE ?= 85k
+BUILDDIR = bin
+TOP ?= top
+VERILOG ?= $(wildcard *.v)
+
+compile: $(BUILDDIR)/toplevel.bit
+
+prog: $(BUILDDIR)/toplevel.bit
+	fujprog $^
+
+dfu: $(BUILDDIR)/toplevel.bit
+	dfu-util -a 0 -D  $^ -R
+
+sim: $(BUILDDIR)/sim.out
+	$^
+
+$(BUILDDIR)/sim.out: $(VERILOG) sim_main.cpp
+	mkdir -p $(BUILDDIR)
+	verilator -Wall --cc $(VERILOG) \
+		--top-module top \
+		--exe sim_main.cpp \
+		--build -CFLAGS "-O2 -std=c++17" \
+		--trace \
+		--Wno-UNUSEDSIGNAL \
+		--Wno-UNDRIVEN \
+		--timing
+	cp obj_dir/Vtop $@
+
+$(BUILDDIR)/toplevel.json: $(VERILOG)
+	mkdir -p $(BUILDDIR)
+	yosys \
+		-p "read -sv $^" \
+		-p "hierarchy -top ${TOP}" \
+		-p "synth_ecp5 -abc9 -json $@" \
+
+$(BUILDDIR)/%.config: $(PIN_DEF) $(BUILDDIR)/toplevel.json
+	nextpnr-ecp5 --${DEVICE} --package CABGA381 --timing-allow-fail --freq 25 --textcfg  $@ --json $(filter-out $<,$^) --lpf $<
+
+$(BUILDDIR)/toplevel.bit: $(BUILDDIR)/toplevel.config
+	ecppack --compress $^ $@
+
+clean:
+	rm -rf ${BUILDDIR} obj_dir
+
+.SECONDARY:
+.PHONY: compile clean prog dfu sim
diff --git a/Verilator_Tests/spi/ulx4m_v002.lpf b/Verilator_Tests/spi/ulx4m_v002.lpf
new file mode 100644
index 0000000..3208109
--- /dev/null
+++ b/Verilator_Tests/spi/ulx4m_v002.lpf
@@ -0,0 +1,397 @@
+BLOCK RESETPATHS;
+BLOCK ASYNCPATHS;
+## ULX4M-LS v0.0.2
+
+# The clock "usb" and "gpdi" sheet
+LOCATE COMP "clk_25mhz" SITE "G2";
+IOBUF  PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33;
+FREQUENCY PORT "clk_25mhz" 25 MHZ;
+
+# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash
+# write to FLASH possible any time from JTAG:
+# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;
+# write to FLASH possible from user bitstream:
+SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
+
+## LED indicators "blinkey" and "gpio" sheet
+LOCATE COMP "led[3]" SITE "C1";
+LOCATE COMP "led[2]" SITE "B3";
+LOCATE COMP "led[1]" SITE "B1";
+LOCATE COMP "led[0]" SITE "B2";
+IOBUF  PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+## Buttons "blinkey" and "gpio" sheet
+LOCATE COMP "btn[1]" SITE "C3";
+LOCATE COMP "btn[2]" SITE "C2";
+IOBUF  PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+
+## SPI Flash chip "flash" sheet
+LOCATE COMP "flash_csn" SITE "R2";
+LOCATE COMP "flash_clk" SITE "U3";
+LOCATE COMP "flash_mosi" SITE "W2";
+LOCATE COMP "flash_miso" SITE "V2";
+LOCATE COMP "flash_holdn" SITE "W1";
+LOCATE COMP "flash_wpn" SITE "Y2";
+#LOCATE COMP "flash_csspin" SITE "AJ3";
+#LOCATE COMP "flash_initn" SITE "AG4";
+#LOCATE COMP "flash_done" SITE "AJ4";
+#LOCATE COMP "flash_programn" SITE "AH4";
+#LOCATE COMP "flash_cfg_select[0]" SITE "AM4";
+#LOCATE COMP "flash_cfg_select[1]" SITE "AL4";
+#LOCATE COMP "flash_cfg_select[2]" SITE "AK4";
+IOBUF  PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+
+## SD card "sdcard", "usb" sheet
+LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14 CM4_GPIO12
+LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi_GPIO15 CM4_GPIO27
+LOCATE COMP "sd_d[0]" SITE "J3"; # sd_dat0_do (MISO) WiFi_GPIO2 CM4_GPIO4
+LOCATE COMP "sd_d[1]" SITE "H1"; # sd_dat1_irq WiFi_GPIO4 CM4_GPIO3
+LOCATE COMP "sd_d[2]" SITE "K1"; # sd_dat2 WiFi_GPIO12  CM4_GPIO2
+LOCATE COMP "sd_d[3]" SITE "K2"; # sd_dat3_csn WiFi_GPIO13  CM4_GPIO14
+LOCATE COMP "sd_wp" SITE "P5"; # not connected
+LOCATE COMP "sd_cdn" SITE "N5"; # not connected
+IOBUF  PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement
+IOBUF  PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+LOCATE COMP "sd_pwr_on" SITE "U17"; # J2_5-  GN14
+IOBUF PORT  "sd_pwr_on" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+## Second USB port "US2" going directly into FPGA "usb", "ram" sheet
+LOCATE COMP "usb_fpga_dp" SITE "E16"; # same on ULX3S and ULX4M
+LOCATE COMP "usb_fpga_dn" SITE "F16"; # same on ULX3S and ULX4M
+IOBUF  PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16;
+IOBUF  PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16;
+LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # single-ended bidirectional same on ULX3S and ULX4M
+LOCATE COMP "usb_fpga_bd_dn" SITE "E15"; # single-ended bidirectional same on ULX3S and ULX4M
+IOBUF  PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+LOCATE COMP "usb_fpga_pu_dp" SITE "A2"; # pull up/down control
+LOCATE COMP "usb_fpga_pu_dn" SITE "A3";
+IOBUF  PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+IOBUF  PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+LOCATE COMP "usb_fpga_otg_id" SITE "A4";
+IOBUF  PORT "usb_fpga_otg_id" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+LOCATE COMP "n_extrst" SITE "U16";
+IOBUF  PORT "n_extrst" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## JTAG ESP-32 "usb" sheet
+# connected to FT231X and ESP-32
+# commented out because those are dedicated pins, not directly useable as GPIO
+# but could be used by some vendor-specific JTAG bridging (boundary scan) module
+#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI   FPGA receives
+#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS  FPGA transmits
+#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR  FPGA receives
+#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD  FPGA receives
+#IOBUF  PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF  PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## SDRAM "ram" sheet
+LOCATE COMP "sdram_clk" SITE "G19";
+LOCATE COMP "sdram_cke" SITE "G20";
+LOCATE COMP "sdram_csn" SITE "P18";
+LOCATE COMP "sdram_wen" SITE "N20";
+LOCATE COMP "sdram_rasn" SITE "M18";
+LOCATE COMP "sdram_casn" SITE "N18";
+LOCATE COMP "sdram_a[0]" SITE "L19";
+LOCATE COMP "sdram_a[1]" SITE "L20";
+LOCATE COMP "sdram_a[2]" SITE "M19";
+LOCATE COMP "sdram_a[3]" SITE "H17";
+LOCATE COMP "sdram_a[4]" SITE "F20";
+LOCATE COMP "sdram_a[5]" SITE "F18";
+LOCATE COMP "sdram_a[6]" SITE "E19";
+LOCATE COMP "sdram_a[7]" SITE "F19";
+LOCATE COMP "sdram_a[8]" SITE "E20";
+LOCATE COMP "sdram_a[9]" SITE "C20";
+LOCATE COMP "sdram_a[10]" SITE "N19";
+LOCATE COMP "sdram_a[11]" SITE "D20";
+LOCATE COMP "sdram_a[12]" SITE "E18";
+LOCATE COMP "sdram_ba[0]" SITE "L18";
+LOCATE COMP "sdram_ba[1]" SITE "M20";
+LOCATE COMP "sdram_dqm[0]" SITE "P20";
+LOCATE COMP "sdram_dqm[1]" SITE "D19";
+LOCATE COMP "sdram_d[0]" SITE "U20";
+LOCATE COMP "sdram_d[1]" SITE "T20";
+LOCATE COMP "sdram_d[2]" SITE "U19";
+LOCATE COMP "sdram_d[3]" SITE "T19";
+LOCATE COMP "sdram_d[4]" SITE "T18";
+LOCATE COMP "sdram_d[5]" SITE "T17";
+LOCATE COMP "sdram_d[6]" SITE "R20";
+LOCATE COMP "sdram_d[7]" SITE "P19";
+LOCATE COMP "sdram_d[8]" SITE "H20";
+LOCATE COMP "sdram_d[9]" SITE "J19";
+LOCATE COMP "sdram_d[10]" SITE "K18";
+LOCATE COMP "sdram_d[11]" SITE "J18";
+LOCATE COMP "sdram_d[12]" SITE "H18";
+LOCATE COMP "sdram_d[13]" SITE "J16";
+LOCATE COMP "sdram_d[14]" SITE "K19";
+LOCATE COMP "sdram_d[15]" SITE "J17";
+IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+# GPDI differential interface (Video) "gpdi" sheet
+LOCATE COMP "gpdi_dp[0]" SITE "F17"; # Blue +
+LOCATE COMP "gpdi_dn[0]" SITE "G18"; # Blue -
+LOCATE COMP "gpdi_dp[1]" SITE "D18"; # Green +
+LOCATE COMP "gpdi_dn[1]" SITE "E17"; # Green -
+LOCATE COMP "gpdi_dp[2]" SITE "C18"; # Red +
+LOCATE COMP "gpdi_dn[2]" SITE "D17"; # Red -
+LOCATE COMP "gpdi_dp[3]" SITE "J20"; # Clock +
+LOCATE COMP "gpdi_dn[3]" SITE "K20"; # Clock -
+#LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet +
+#LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet -
+LOCATE COMP "gpdi_cec" SITE "A18";
+#LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC
+#LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12
+IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+LOCATE COMP "gpdi_dp[4]" SITE "B9"; # Blue +
+#LOCATE COMP "gpdi_dn[4]" SITE "C10"; # Blue -
+LOCATE COMP "gpdi_dp[5]" SITE "A7"; # Green +
+#LOCATE COMP "gpdi_dn[5]" SITE "A8"; # Green -
+LOCATE COMP "gpdi_dp[6]" SITE "C8"; # Red +
+#LOCATE COMP "gpdi_dn[6]" SITE "B8"; # Red -
+LOCATE COMP "gpdi_dp[7]" SITE "B11"; # Clock +
+#LOCATE COMP "gpdi_dn[7]" SITE "C11"; # Clock -
+IOBUF PORT "gpdi_dp[4]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dn[4]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dp[5]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dn[5]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dp[6]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dn[6]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dp[7]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dn[7]" IO_TYPE=LVCMOS33D DRIVE=4;
+
+# wifi - do not use together with CM4 GPIO
+LOCATE COMP "wifi_gpio0" SITE "U1";
+LOCATE COMP "wifi_gpio2" SITE "K4"; # sd_d0_do (MISO) WiFi GPIO2
+LOCATE COMP "wifi_gpio4" SITE "J5"; # sd_d1_irq WiFi GPIO4
+LOCATE COMP "wifi_gpio5" SITE "U5"; #
+LOCATE COMP "wifi_gpio12" SITE "K5"; # sd_d2 WiFi_GPIO12
+LOCATE COMP "wifi_gpio13" SITE "L4"; # sd_d3_csn WiFi_GPIO13
+LOCATE COMP "wifi_gpio14" SITE "L5"; # sd_clk WiFi_GPIO14
+LOCATE COMP "wifi_gpio15" SITE "N16"; # sd_cmd_di (MOSI) WiFi GPIO15
+LOCATE COMP "wifi_gpio19" SITE "P4";
+LOCATE COMP "wifi_gpio21" SITE "P17";
+LOCATE COMP "wifi_gpio22" SITE "P16";
+LOCATE COMP "wifi_gpio25" SITE "L16";
+LOCATE COMP "wifi_gpio26" SITE "N17";
+LOCATE COMP "wifi_gpio27" SITE "G16";
+LOCATE COMP "wifi_gpio33" SITE "H16";
+LOCATE COMP "wifi_gpio34" SITE "V4";
+LOCATE COMP "wifi_gpio35" SITE "N17";
+
+IOBUF  PORT "wifi_gpio0" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio2" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # pull down or drive 0 for esp32 programming
+IOBUF  PORT "wifi_gpio4" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio5" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio12" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio13" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # pull down or drive 0 for esp32 programming
+IOBUF  PORT "wifi_gpio14" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio15" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio19" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio21" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio22" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio25" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio26" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio27" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio33" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio34" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_gpio35" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+LOCATE COMP "ftdi_txden" SITE "T1"; # FTDI_TXDEN
+LOCATE COMP "LED1_HAT" SITE "N5"; # LED1 on HAT
+LOCATE COMP "wifi_en" SITE "U18";# WIFI_EN
+LOCATE COMP "ftdi_txd" SITE "N4"; # FTDI_TXD
+LOCATE COMP "ftdi_rxd" SITE "N3"; # FTDI_RXD
+LOCATE COMP "wifi_txd" SITE "P5"; # WIFI_TXD
+LOCATE COMP "wifi_rxd" SITE "V1"; # WIFI_RXD
+
+IOBUF  PORT "ftdi_txden" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "LED1_HAT" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "ftdi_txd" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "ftdi_rxd" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+LOCATE COMP "btn[3]" SITE "E3";
+LOCATE COMP "btn[4]" SITE "E4";
+LOCATE COMP "btn[5]" SITE "E5";
+LOCATE COMP "btn[6]" SITE "H5";
+LOCATE COMP "btn[0]" SITE "H4";
+LOCATE COMP "nc1" SITE "F2";
+LOCATE COMP "sw" SITE "G3";
+IOBUF  PORT "btn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "btn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "btn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "btn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "btn[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "nc1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "sw[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## CM4 GPIO
+LOCATE COMP "gpio[0]" SITE "R16"; # SDA0 - WIFI_GPIO21
+LOCATE COMP "gpio[1]" SITE "R17"; # SCL0 - WIFI_GPIO22
+LOCATE COMP "gpio[2]" SITE "K5";  # SD_D2 - ESP32 SD share
+LOCATE COMP "gpio[3]" SITE "J5";  # SD_D1 - ESP32 SD share
+LOCATE COMP "gpio[4]" SITE "K4";  # SD_D0 - ESP32 SD share
+LOCATE COMP "gpio[5]" SITE "H16"; # WIFI_GPIO33
+LOCATE COMP "gpio[6]" SITE "R1";  # BTN1 on HAT
+LOCATE COMP "gpio[7]" SITE "P3";  # BTN2 on HAT
+LOCATE COMP "gpio[8]" SITE "P4";  # WIFI_GPIO19
+LOCATE COMP "gpio[9]" SITE "G16"; # WIFI_GPIO27
+LOCATE COMP "gpio[10]" SITE "N17";# WIFI_GPIO26
+LOCATE COMP "gpio[11]" SITE "L16";# WIFI_GPIO25
+LOCATE COMP "gpio[12]" SITE "C4"; # FPGA TDI  do not use - not connected!
+LOCATE COMP "gpio[13]" SITE "T1"; # FTDI_TXDEN
+LOCATE COMP "gpio[14]" SITE "L4"; # SD_D3 - ESP32 SD share
+LOCATE COMP "gpio[15]" SITE "L5"; # SD_CLK - ESP32 SD share
+LOCATE COMP "gpio[16]" SITE "B4"; # FPGA TDO do not use - not connected!
+LOCATE COMP "gpio[17]" SITE "M17";# WIFI_GPIO35
+LOCATE COMP "gpio[18]" SITE "N5"; # LED1 on HAT
+LOCATE COMP "gpio[19]" SITE "U1"; # WIFI_GPIO0
+LOCATE COMP "gpio[20]" SITE "E4"; # FPGA TCK do not use - not connected!
+LOCATE COMP "gpio[21]" SITE "D5"; # FPGA TMS do not use - not connected!
+LOCATE COMP "gpio[22]" SITE "U18";# WIFI_EN
+LOCATE COMP "gpio[23]" SITE "N4"; # FTDI_TXD
+LOCATE COMP "gpio[24]" SITE "N3"; # FTDI_RXD
+LOCATE COMP "gpio[25]" SITE "P5"; # WIFI_TXD
+LOCATE COMP "gpio[26]" SITE "V1"; # WIFI_RXD
+LOCATE COMP "gpio[27]" SITE "N16";# SD_CMD - ESP32 SD share
+IOBUF  PORT "gpio[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[16]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[17]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[18]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[19]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[20]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[21]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[22]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[23]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[24]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[25]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[26]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "gpio[27]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+## DSI
+#
+LOCATE COMP "dsiRX0_dp[0]" SITE "B12"; # Clk +
+LOCATE COMP "dsiRX0_dn[0]" SITE "C12"; # Clk -
+LOCATE COMP "dsiRX0_dp[1]" SITE "A12"; # DSI RX D0 +
+LOCATE COMP "dsiRX0_dn[1]" SITE "A13"; # DSI RX D0 -
+LOCATE COMP "dsiRX0_dp[2]" SITE "B13"; # DSI RX D1 +
+LOCATE COMP "dsiRX0_dn[2]" SITE "C13"; # DSI RX D1 -
+LOCATE COMP "dsiTX0_dp[0]" SITE "D12"; # Clk +
+LOCATE COMP "dsiTX0_dn[0]" SITE "E12"; # Clk -
+LOCATE COMP "dsiTX0_dp[1]" SITE "D13"; # DSI TX D0 +
+LOCATE COMP "dsiTX0_dn[1]" SITE "E13"; # DSI TX D0 -
+LOCATE COMP "dsiTX0_dp[2]" SITE "A14"; # DSI TX D1 +
+LOCATE COMP "dsiTX0_dn[2]" SITE "C14"; # DSI TX D1 -
+IOBUF PORT "dsiRX0_dp[0]" IO_TYPE=LVCMOS12 ;
+IOBUF PORT "dsiRX0_dn[0]" IO_TYPE=LVCMOS12 ;
+IOBUF PORT "dsiRX0_dp[1]" IO_TYPE=LVCMOS12 ;
+IOBUF PORT "dsiRX0_dn[1]" IO_TYPE=LVCMOS12 ;
+IOBUF PORT "dsiRX0_dp[2]" IO_TYPE=LVCMOS12 ;
+IOBUF PORT "dsiRX0_dn[2]" IO_TYPE=LVCMOS12 ;
+IOBUF PORT "dsiTX0_dp[0]" IO_TYPE=LVCMOS12 ;
+IOBUF PORT "dsiTX0_dp[0]" IO_TYPE=LVCMOS12 ;
+IOBUF PORT "dsiTX0_dp[1]" IO_TYPE=LVCMOS12 ;
+IOBUF PORT "dsiTX0_dp[1]" IO_TYPE=LVCMOS12 ;
+IOBUF PORT "dsiTX0_dp[2]" IO_TYPE=LVCMOS12 ;
+IOBUF PORT "dsiTX0_dp[2]" IO_TYPE=LVCMOS12 ;
+
+## PROGRAMN (reload bitstream from FLASH, exit from bootloader)
+# PCB v2.0.5 and higher
+LOCATE COMP "user_programn" SITE "M4";
+IOBUF  PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5)
+# on PCB v1.7 shutdown is not connected to FPGA
+LOCATE COMP "shutdown" SITE "G16"; # FPGA receives
+IOBUF  PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
diff --git a/Verilator_Tests/spi/wave.vcd b/Verilator_Tests/spi/wave.vcd
new file mode 100644
index 0000000..5e2aad0
--- /dev/null
+++ b/Verilator_Tests/spi/wave.vcd
@@ -0,0 +1,730 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module TOP $end
+  $var wire 1 # clk_25mhz $end
+  $var wire 1 $ spi_clk $end
+  $var wire 1 % spi_mosi $end
+  $var wire 1 & spi_miso $end
+  $var wire 1 ' spi_cs $end
+  $scope module top $end
+   $var wire 1 # clk_25mhz $end
+   $var wire 1 $ spi_clk $end
+   $var wire 1 % spi_mosi $end
+   $var wire 1 & spi_miso $end
+   $var wire 1 ' spi_cs $end
+   $var wire 8 ( mosi_shift [7:0] $end
+   $var wire 4 ) bit_counter [3:0] $end
+   $var wire 1 * spi_clk_en $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+1#
+0$
+0%
+0&
+0'
+b01101011 (
+b0000 )
+0*
+#20
+0#
+#40
+1#
+1$
+b11010110 (
+b0001 )
+#60
+0#
+#80
+1#
+0$
+#100
+0#
+#120
+1#
+1$
+1%
+b10101100 (
+b0010 )
+#140
+0#
+#160
+1#
+0$
+#180
+0#
+#200
+1#
+1$
+b01011000 (
+b0011 )
+#220
+0#
+#240
+1#
+0$
+#260
+0#
+#280
+1#
+1$
+0%
+b10110000 (
+b0100 )
+#300
+0#
+#320
+1#
+0$
+#340
+0#
+#360
+1#
+1$
+1%
+b01100000 (
+b0101 )
+#380
+0#
+#400
+1#
+0$
+#420
+0#
+#440
+1#
+1$
+0%
+b11000000 (
+b0110 )
+#460
+0#
+#480
+1#
+0$
+#500
+0#
+#520
+1#
+1$
+1%
+b10000000 (
+b0111 )
+#540
+0#
+#560
+1#
+0$
+#580
+0#
+#600
+1#
+1$
+b00000000 (
+b1000 )
+#620
+0#
+#640
+1#
+0$
+#660
+0#
+#680
+1#
+1$
+0%
+b1001 )
+#700
+0#
+#720
+1#
+0$
+#740
+0#
+#760
+1#
+1$
+b1010 )
+#780
+0#
+#800
+1#
+0$
+#820
+0#
+#840
+1#
+1$
+b1011 )
+#860
+0#
+#880
+1#
+0$
+#900
+0#
+#920
+1#
+1$
+b1100 )
+#940
+0#
+#960
+1#
+0$
+#980
+0#
+#1000
+1#
+1$
+b1101 )
+#1020
+0#
+#1040
+1#
+0$
+#1060
+0#
+#1080
+1#
+1$
+b1110 )
+#1100
+0#
+#1120
+1#
+0$
+#1140
+0#
+#1160
+1#
+1$
+b1111 )
+#1180
+0#
+#1200
+1#
+0$
+#1220
+0#
+#1240
+1#
+1$
+b0000 )
+#1260
+0#
+#1280
+1#
+0$
+#1300
+0#
+#1320
+1#
+1$
+b0001 )
+#1340
+0#
+#1360
+1#
+0$
+#1380
+0#
+#1400
+1#
+1$
+b0010 )
+#1420
+0#
+#1440
+1#
+0$
+#1460
+0#
+#1480
+1#
+1$
+b0011 )
+#1500
+0#
+#1520
+1#
+0$
+#1540
+0#
+#1560
+1#
+1$
+b0100 )
+#1580
+0#
+#1600
+1#
+0$
+#1620
+0#
+#1640
+1#
+1$
+b0101 )
+#1660
+0#
+#1680
+1#
+0$
+#1700
+0#
+#1720
+1#
+1$
+b0110 )
+#1740
+0#
+#1760
+1#
+0$
+#1780
+0#
+#1800
+1#
+1$
+b0111 )
+#1820
+0#
+#1840
+1#
+0$
+#1860
+0#
+#1880
+1#
+1$
+b1000 )
+#1900
+0#
+#1920
+1#
+0$
+#1940
+0#
+#1960
+1#
+1$
+b1001 )
+#1980
+0#
+#2000
+1#
+0$
+#2020
+0#
+#2040
+1#
+1$
+b1010 )
+#2060
+0#
+#2080
+1#
+0$
+#2100
+0#
+#2120
+1#
+1$
+b1011 )
+#2140
+0#
+#2160
+1#
+0$
+#2180
+0#
+#2200
+1#
+1$
+b1100 )
+#2220
+0#
+#2240
+1#
+0$
+#2260
+0#
+#2280
+1#
+1$
+b1101 )
+#2300
+0#
+#2320
+1#
+0$
+#2340
+0#
+#2360
+1#
+1$
+b1110 )
+#2380
+0#
+#2400
+1#
+0$
+#2420
+0#
+#2440
+1#
+1$
+b1111 )
+#2460
+0#
+#2480
+1#
+0$
+#2500
+0#
+#2520
+1#
+1$
+b0000 )
+#2540
+0#
+#2560
+1#
+0$
+#2580
+0#
+#2600
+1#
+1$
+b0001 )
+#2620
+0#
+#2640
+1#
+0$
+#2660
+0#
+#2680
+1#
+1$
+b0010 )
+#2700
+0#
+#2720
+1#
+0$
+#2740
+0#
+#2760
+1#
+1$
+b0011 )
+#2780
+0#
+#2800
+1#
+0$
+#2820
+0#
+#2840
+1#
+1$
+b0100 )
+#2860
+0#
+#2880
+1#
+0$
+#2900
+0#
+#2920
+1#
+1$
+b0101 )
+#2940
+0#
+#2960
+1#
+0$
+#2980
+0#
+#3000
+1#
+1$
+b0110 )
+#3020
+0#
+#3040
+1#
+0$
+#3060
+0#
+#3080
+1#
+1$
+b0111 )
+#3100
+0#
+#3120
+1#
+0$
+#3140
+0#
+#3160
+1#
+1$
+b1000 )
+#3180
+0#
+#3200
+1#
+0$
+#3220
+0#
+#3240
+1#
+1$
+b1001 )
+#3260
+0#
+#3280
+1#
+0$
+#3300
+0#
+#3320
+1#
+1$
+b1010 )
+#3340
+0#
+#3360
+1#
+0$
+#3380
+0#
+#3400
+1#
+1$
+b1011 )
+#3420
+0#
+#3440
+1#
+0$
+#3460
+0#
+#3480
+1#
+1$
+b1100 )
+#3500
+0#
+#3520
+1#
+0$
+#3540
+0#
+#3560
+1#
+1$
+b1101 )
+#3580
+0#
+#3600
+1#
+0$
+#3620
+0#
+#3640
+1#
+1$
+b1110 )
+#3660
+0#
+#3680
+1#
+0$
+#3700
+0#
+#3720
+1#
+1$
+b1111 )
+#3740
+0#
+#3760
+1#
+0$
+#3780
+0#
+#3800
+1#
+1$
+b0000 )
+#3820
+0#
+#3840
+1#
+0$
+#3860
+0#
+#3880
+1#
+1$
+b0001 )
+#3900
+0#
+#3920
+1#
+0$
+#3940
+0#
+#3960
+1#
+1$
+b0010 )
+#3980
+0#
+#4000
+1#
+0$
+#4020
+0#
+#4040
+1#
+1$
+b0011 )
+#4060
+0#
+#4080
+1#
+0$
+#4100
+0#
+#4120
+1#
+1$
+b0100 )
+#4140
+0#
+#4160
+1#
+0$
+#4180
+0#
+#4200
+1#
+1$
+b0101 )
+#4220
+0#
+#4240
+1#
+0$
+#4260
+0#
+#4280
+1#
+1$
+b0110 )
+#4300
+0#
+#4320
+1#
+0$
+#4340
+0#
+#4360
+1#
+1$
+b0111 )
+#4380
+0#
+#4400
+1#
+0$
+#4420
+0#
+#4440
+1#
+1$
+b1000 )
+#4460
+0#
+#4480
+1#
+0$
+#4500
+0#
+#4520
+1#
+1$
+b1001 )
+#4540
+0#
+#4560
+1#
+0$
+#4580
+0#
+#4600
+1#
+1$
+b1010 )
+#4620
+0#
+#4640
+1#
+0$
+#4660
+0#
+#4680
+1#
+1$
+b1011 )
+#4700
+0#
+#4720
+1#
+0$
+#4740
+0#
+#4760
+1#
+1$
+b1100 )
+#4780
+0#
+#4800
+1#
+0$
+#4820
+0#
+#4840
+1#
+1$
+b1101 )
+#4860
+0#
+#4880
+1#
+0$
+#4900
+0#
+#4920
+1#
+1$
+b1110 )
+#4940
+0#
+#4960
+1#
+0$
+#4980
+0#
+#4999