From 63fa6db8d60232a95c7e8c6d95faa15a18414853 Mon Sep 17 00:00:00 2001
From: Benjamin Kyd <benjaminkyd@gmail.com>
Date: Sun, 5 Jun 2022 00:55:14 +0100
Subject: [PATCH] reg

---
 Max10_VGA/Max10_VGA.qsf      |   4 ++--
 Max10_VGA/Max10_VGA.qws      | Bin 3690 -> 0 bytes
 Max10_VGA/top.sv             |   1 +
 Max10_VGA/top_tb.sv          |  18 +++++++++---------
 Max10_VGA/vga_controller.sv  |   9 ++++++++-
 Max10_VGA/vga_test_screen.sv |   7 +++++--
 6 files changed, 25 insertions(+), 14 deletions(-)
 delete mode 100644 Max10_VGA/Max10_VGA.qws

diff --git a/Max10_VGA/Max10_VGA.qsf b/Max10_VGA/Max10_VGA.qsf
index d03bc25..84abb38 100644
--- a/Max10_VGA/Max10_VGA.qsf
+++ b/Max10_VGA/Max10_VGA.qsf
@@ -20,10 +20,10 @@ set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "ViewDraw (Symbol)"
 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VIEWDRAW -section_id eda_board_design_symbol
 set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "IBIS (Signal Integrity)"
 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT IBIS -section_id eda_board_design_signal_integrity
-set_global_assignment -name VCCA_USER_VOLTAGE 3.0V
+set_global_assignment -name VCCA_USER_VOLTAGE 3.3V
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
diff --git a/Max10_VGA/Max10_VGA.qws b/Max10_VGA/Max10_VGA.qws
deleted file mode 100644
index 054170651595d3a0514468132c42f97950a3c296..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 3690
zcmeH~y=zlZ7{;HQG`53-IEaFvNYNmqCQVXx@uQ$Fx`?=j+vK*E)Fi!)wjjm0`hPgP
zIqK3uaB+2V^KTH0#@~BxavPH%H3TXpC!CM>+~@r`=R7^<?X9$W<*YX3YfDX)w5_^A
zRgoIZl@$O=Q47pJ1JQ78Nvm2%D*$&z4?ylHr!4x9bx*gofMx}ZbR3;JS_>ebBhS;W
zfiE#{+U9c$bchtF7UM3&xH9@Ra3TGM^BKmdlU?g(Z6%&PhM)U-p=-qC6Zs;R^RyXe
zuHtKnQI21QngNkTH_Ir?Z;|Q~`6_Lm)--p=UBBl^UJ30ERX?qflJBV>7|e9*9Q|Co
zE6^!Hy~qjz{5N%8%WltYA8SaD=xrxfh%hv$Iuz@><%I5{8n8TrlvN!CA~IP`>met(
zrYGZgGQ(zM-UZblxW9x7ZYb0wQ)b{YighBeH9q}!Gt1tW&!2>`PUm|IbM)<-Z15T6
zSBU43Zy=v$Z0<DM8u7&_Q|7pRNRVg$d}_wYWk-*KiV&#C+;#TWa2cp%RLMds-_-)W
z(atFI2ldUZ_nM}k3aKRy`y-P_g9=86v8iwh4h38zM)*7I@46#H=#FcE;FD$zVRuWa
z$bo$8Nx1!G)nr@SY|BPbiIJ0L&4Dh+k!(urK(RN3H)WF!l}(9v9K<EwP1uy=F&dO3
z1{s@%zD$};2Y5!OT<UvI-O&tOH;2n5SYl;{cf<P%V_Hs(<w$Z|8vHV8E{#aGrri0j
zxx+nV#qJ@;odG%e+PjDPkuH6%kn32^W4$HwmJ3D6^kDjI8P9O~TmYRT8`|ytJ$Y~O
z5$8YdWhXG^yuG$dC4VqZljt}2H)PZOi%=&cE8*SxDx+=kf(q$spk_~h52cdjz}N}R
l7V^<}0d0k2=Tk|P&A_BmYfMq>SxdZ(p0!c(ev-70{0&ZISlj>r

diff --git a/Max10_VGA/top.sv b/Max10_VGA/top.sv
index bed03df..78ed605 100644
--- a/Max10_VGA/top.sv
+++ b/Max10_VGA/top.sv
@@ -12,6 +12,7 @@ module top (
 	
 	wire vsync_pulse, hsync_pulse;
 	
+	// 1111111111 = NO DRAW
 	wire [10:0] scan_pos_x;
 	wire [10:0] scan_pos_y;
 	
diff --git a/Max10_VGA/top_tb.sv b/Max10_VGA/top_tb.sv
index 8c72f70..95e9458 100644
--- a/Max10_VGA/top_tb.sv
+++ b/Max10_VGA/top_tb.sv
@@ -4,20 +4,12 @@ module tb();
 	reg clk = 1'b0;
 	
 	wire v_h_sync;
-	wire v_v_sync;
+	wire v_v_sync;////////////////////////////////
 	
 	wire [10:0] scan_pos_x;
 	wire [10:0] scan_pos_y;
 	
 	wire [2:0] rgb;
-
-	VGA_Signal_Gen VGA_Signal_Gen_Inst(
-		.pixel_clk(clk),
-		.scan_x(scan_pos_x),
-		.scan_y(scan_pos_y),
-		.h_sync(v_h_sync),
-		.v_sync(v_v_sync)
-	);
 	
 	VGA_Test_Screen VGA_Test_Screen_Inst(
 		.pixel_clk(clk),
@@ -26,6 +18,14 @@ module tb();
 		.rgb(rgb)
 	);
 	
+	VGA_Signal_Gen VGA_Signal_Gen_Inst(
+		.pixel_clk(clk),
+		.scan_x(scan_pos_x),
+		.scan_y(scan_pos_y),
+		.h_sync(v_h_sync),
+		.v_sync(v_v_sync)
+	);
+	
 	// 25MHz clock
 	always #20 clk <= ~clk;
 	
diff --git a/Max10_VGA/vga_controller.sv b/Max10_VGA/vga_controller.sv
index 350115a..bb3a778 100644
--- a/Max10_VGA/vga_controller.sv
+++ b/Max10_VGA/vga_controller.sv
@@ -1,4 +1,8 @@
-module VGA_Signal_Gen(
+module VGA_Signal_Gen
+ #(parameter TOTAL_COLS  = 800, 
+   parameter TOTAL_ROWS  = 525,
+   parameter ACTIVE_COLS = 640, 
+   parameter ACTIVE_ROWS = 480)(
 	input wire pixel_clk,
 	output wire [10:0] scan_x,
 	output wire [10:0] scan_y,
@@ -30,5 +34,8 @@ module VGA_Signal_Gen(
 	// generate sync pulses
 	assign h_sync = ~(h_counter <= 96);
 	assign v_sync = ~(v_counter <= 2);
+	
+	assign scan_x = h_counter + 48;
+	assign scan_y = v_counter + 33;
 
 endmodule
diff --git a/Max10_VGA/vga_test_screen.sv b/Max10_VGA/vga_test_screen.sv
index bc44030..c40d846 100644
--- a/Max10_VGA/vga_test_screen.sv
+++ b/Max10_VGA/vga_test_screen.sv
@@ -2,11 +2,14 @@ module VGA_Test_Screen(
 	input wire pixel_clk,
 	input wire [10:0] x,
 	input wire [10:0] y,
-	output wire [2:0] rgb
+	output reg [2:0] rgb
 );
 
+
 	always @(posedge pixel_clk) begin
-		rgb[2:2] = 1;
+		if (x > 20) begin
+			rgb[1] <= 1;
+		end
 	end
 	
 endmodule