epic testbenches

.gitignore

@@ -4,3 +4,5 @@ build/
 bin/
 .obj_dir/
 obj_dir/
+.nvim/
+.cache/

Verilator_Tests/clk/sim_main.cpp

@@ -13,7 +13,7 @@ int main(int argc, char** argv) {
     tfp->open("wave.vcd");
 
     int clk = 0;
-    for (int time = 0; time < 500; time++) {
+    for (int time = 0; time < 50000; time++) {
         // Toggle clk every 20 time units (simulate 25 MHz)
         if ((time % 20) == 0)
             clk = !clk;

Verilator_Tests/clk/top.v

@@ -1,6 +1,15 @@
 module top (
     input clk_25mhz,
-    output [3:0] led
+
+    output h_sync,
+    output v_sync,
+
+
+    output [3:0] r,
+    output [3:0] g,
+    output [3:0] b
 );
-    assign led[0] = clk_25mhz;
+
+    
+
 endmodule

Verilator_Tests/clk/top_tb.v

@@ -1,13 +1,24 @@
+// Copyright 2025 Benjamin Kyd, All Rights Reserved
+
 `timescale 1ns / 1ps
 
 module top_tb;
 
     reg clk_25mhz = 0;
-    wire [3:0] led;
+
+    wire h_sync, v_sync;
+
+    wire [3:0] r;
+    wire [3:0] g;
+    wire [3:0] b;
 
     top uut (
         .clk_25mhz(clk_25mhz),
-        .led(led)
+        .h_sync(h_sync),
+        .v_sync(v_sync),
+        .r(r),
+        .g(g),
+        .b(b)
     );
 
     always #20 clk_25mhz = ~clk_25mhz;