From 9f12c776eeaa2e4cba46cadc055a228e5ae8f8d2 Mon Sep 17 00:00:00 2001
From: Ben Kyd <ben@benkyd.co.uk>
Date: Wed, 9 Jul 2025 22:33:12 +0100
Subject: [PATCH] not good nuf

---
 Verilator_Tests/spi/top.v | 39 ++++++++++++++++++++++++++++++++++++---
 1 file changed, 36 insertions(+), 3 deletions(-)

diff --git a/Verilator_Tests/spi/top.v b/Verilator_Tests/spi/top.v
index 7ebf62d..c77e3da 100644
--- a/Verilator_Tests/spi/top.v
+++ b/Verilator_Tests/spi/top.v
@@ -1,19 +1,51 @@
 module top (
     input wire clk_25mhz,
 
+    output wire spi_clk,
+    output wire spi_mosi,
+    input wire spi_miso,
+    output wire spi_cs
+);
+
+reg[7:0] miso;
+reg[7:0] mosi = 8'b01101011;
+
+spi_master spimaster0(
+    .clk_25mhz(clk_25mhz),
+    .spi_clk(spi_clk),
+    .data_in(mosi),
+    .spi_miso(spi_miso),
+    .data_out(mosi),
+    .spi_mosi(spi_mosi),
+    .spi_cs(spi_cs)
+);
+
+endmodule
+
+
+module spi_master (
+    input wire clk_25mhz,
+
     output reg spi_clk = 0,
 
-    output reg spi_mosi = 0,
-    input reg spi_miso = 0,
+    output reg[7:0] data_in,
+    output reg spi_miso = 0,
+
+    input reg[7:0] data_out,
+    input reg spi_mosi = 0,
 
     output wire spi_cs
 );
 
+
 assign spi_cs = 0;  // Always selected (for test)
 
 reg [7:0] mosi_shift = 8'b01101011;  // Example byte
 reg [3:0] bit_counter = 0;
-reg spi_clk_en = 0;
+reg spi_clk_en = 1;
+
+localparam TRANSFERRING = 0, IDLE = 1;
+wire spi_state = IDLE;
 
 always_ff @(posedge clk_25mhz) begin
     spi_clk <= ~spi_clk;
@@ -27,3 +59,4 @@ always_ff @(posedge clk_25mhz) begin
 end
 
 endmodule
+