diff --git a/.nvim/svlangserver/index.json b/.nvim/svlangserver/index.json
new file mode 100644
index 0000000..f0856df
--- /dev/null
+++ b/.nvim/svlangserver/index.json
@@ -0,0 +1 @@
+{"version":"1.1.0","info":[["/home/benk/projects/fpga-basics/Max10_RT/PLL_bb.v",[[[[[["PLL",[[34,0],[36,5]],[[34,7],[34,10]],[],["module"]],[42,0]],[[["inclk0",[[38,9],[38,15]],[[38,9],[38,15]],["PLL"],["port"]],["c0",[[36,1],[36,3]],[[36,1],[36,3]],["PLL"],["port","inclk0"]],["c0",[[39,10],[39,12]],[[39,10],[39,12]],["PLL"],["port"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_RT/PLL_inst.v",[[null,null,null,null,[["PLL_inst",[[0,0],[3,2]],[[0,4],[0,12]],[],["instance","PLL"]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_RT/PLL.v",[[[[[["PLL",[[39,0],[41,5]],[[39,7],[39,10]],[],["module"]],[149,0]],[[["inclk0",[[43,9],[43,15]],[[43,9],[43,15]],["PLL"],["port"]],["c0",[[41,1],[41,3]],[[41,1],[41,3]],["PLL"],["port","inclk0"]],["c0",[[44,10],[44,12]],[[44,10],[44,12]],["PLL"],["port"]],["sub_wire2",[[46,1],[46,28]],[[46,12],[46,21]],["PLL"],["variable","wire"]],["sub_wire3",[[47,1],[47,21]],[[47,12],[47,21]],["PLL"],["variable","wire"]],["sub_wire0",[[48,1],[48,25]],[[48,7],[48,16]],["PLL"],["variable","wire"]],["sub_wire1",[[49,1],[49,46]],[[49,12],[49,21]],["PLL"],["variable","wire"]],["sub_wire4",[[50,1],[50,38]],[[50,12],[50,21]],["PLL"],["variable","wire"]],["c0",[[51,1],[51,21]],[[51,7],[51,9]],["PLL"],["variable","wire"]],["altpll_component",[[53,1],[90,22]],[[53,8],[53,24]],["PLL"],["instance","altpll"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_RT/raytracer.sv",[[[[[["Raytracer",[[0,0],[5,2]],[[0,7],[0,16]],[],["module"]],[7,9]],[[["pixel_clk",[[1,1],[1,21]],[[1,12],[1,21]],["Raytracer"],["port","wire"]],["x",[[2,1],[2,19]],[[2,18],[2,19]],["Raytracer"],["port","reg"]],["y",[[3,1],[3,19]],[[3,18],[3,19]],["Raytracer"],["port","reg"]],["rgb",[[4,1],[4,21]],[[4,18],[4,21]],["Raytracer"],["port","reg"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_RT/top_tb.sv",[[[[[["tb",[[2,0],[2,12]],[[2,7],[2,9]],[],["module"]],[37,9]],[[["clk",[[3,1],[3,15]],[[3,5],[3,8]],["tb"],["variable","reg"]],["v_h_sync",[[5,1],[5,14]],[[5,6],[5,14]],["tb"],["variable","wire"]],["v_v_sync",[[6,1],[6,14]],[[6,6],[6,14]],["tb"],["variable","wire"]],["scan_pos_x",[[8,1],[8,23]],[[8,13],[8,23]],["tb"],["variable","wire"]],["scan_pos_y",[[9,1],[9,23]],[[9,13],[9,23]],["tb"],["variable","wire"]],["rgb",[[11,1],[11,15]],[[11,12],[11,15]],["tb"],["variable","wire"]],["VGA_Test_Screen_Inst",[[13,1],[18,2]],[[13,17],[13,37]],["tb"],["instance","VGA_Test_Screen"]],["VGA_Signal_Gen_Inst",[[20,1],[26,2]],[[20,16],[20,35]],["tb"],["instance","VGA_Signal_Gen"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_RT/top.sv",[[[[[["top",[[0,0],[7,2]],[[0,7],[0,10]],[],["module"]],[44,9]],[[["clk12m",[[2,1],[2,19]],[[2,13],[2,19]],["top"],["port","logic"]],["gpio_d",[[4,1],[4,27]],[[4,21],[4,27]],["top"],["port","logic"]],["led",[[6,1],[6,23]],[[6,20],[6,23]],["top"],["port","logic"]],["pixel_clk",[[8,1],[8,15]],[[8,6],[8,15]],["top"],["variable","wire"]],["p_clk_pll",[[10,1],[10,34]],[[10,5],[10,14]],["top"],["instance","PLL"]],["rgb",[[12,1],[12,15]],[[12,12],[12,15]],["top"],["variable","wire"]],["hcounter",[[14,1],[14,20]],[[14,12],[14,20]],["top"],["variable","wire"]],["vcounter",[[15,1],[15,20]],[[15,12],[15,20]],["top"],["variable","wire"]],["hsync",[[17,1],[17,11]],[[17,6],[17,11]],["top"],["variable","wire"]],["vsync",[[18,1],[18,11]],[[18,6],[18,11]],["top"],["variable","wire"]],["VGA_Signal_Gen_Inst",[[20,1],[26,2]],[[20,16],[20,35]],["top"],["instance","VGA_Signal_Gen"]],["VGA_Test_Screen_Inst",[[28,1],[33,2]],[[28,17],[28,37]],["top"],["instance","VGA_Test_Screen"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_RT/vga_controller.sv",[[[[[["VGA_Signal_Gen",[[0,0],[6,2]],[[0,7],[0,21]],[],["module"]],[33,9]],[[["pixel_clk",[[1,1],[1,21]],[[1,12],[1,21]],["VGA_Signal_Gen"],["port","wire"]],["hcounter",[[2,1],[2,26]],[[2,18],[2,26]],["VGA_Signal_Gen"],["port","reg"]],["vcounter",[[3,1],[3,26]],[[3,18],[3,26]],["VGA_Signal_Gen"],["port","reg"]],["hsync",[[4,1],[4,18]],[[4,13],[4,18]],["VGA_Signal_Gen"],["port","wire"]],["vsync",[[5,1],[5,18]],[[5,13],[5,18]],["VGA_Signal_Gen"],["port","wire"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_RT/vga_test_screen.sv",[[[[[["VGA_Test_Screen",[[0,0],[5,2]],[[0,7],[0,22]],[],["module"]],[30,9]],[[["pixel_clk",[[1,1],[1,21]],[[1,12],[1,21]],["VGA_Test_Screen"],["port","wire"]],["x",[[2,1],[2,19]],[[2,18],[2,19]],["VGA_Test_Screen"],["port","reg"]],["y",[[3,1],[3,19]],[[3,18],[3,19]],["VGA_Test_Screen"],["port","reg"]],["rgb",[[4,1],[4,21]],[[4,18],[4,21]],["VGA_Test_Screen"],["port","reg"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_VGA/PLL_bb.v",[[[[[["PLL",[[34,0],[36,5]],[[34,7],[34,10]],[],["module"]],[42,0]],[[["inclk0",[[38,9],[38,15]],[[38,9],[38,15]],["PLL"],["port"]],["c0",[[36,1],[36,3]],[[36,1],[36,3]],["PLL"],["port","inclk0"]],["c0",[[39,10],[39,12]],[[39,10],[39,12]],["PLL"],["port"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_VGA/PLL_inst.v",[[null,null,null,null,[["PLL_inst",[[0,0],[3,2]],[[0,4],[0,12]],[],["instance","PLL"]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_VGA/PLL.v",[[[[[["PLL",[[39,0],[41,5]],[[39,7],[39,10]],[],["module"]],[149,0]],[[["inclk0",[[43,9],[43,15]],[[43,9],[43,15]],["PLL"],["port"]],["c0",[[41,1],[41,3]],[[41,1],[41,3]],["PLL"],["port","inclk0"]],["c0",[[44,10],[44,12]],[[44,10],[44,12]],["PLL"],["port"]],["sub_wire2",[[46,1],[46,28]],[[46,12],[46,21]],["PLL"],["variable","wire"]],["sub_wire3",[[47,1],[47,21]],[[47,12],[47,21]],["PLL"],["variable","wire"]],["sub_wire0",[[48,1],[48,25]],[[48,7],[48,16]],["PLL"],["variable","wire"]],["sub_wire1",[[49,1],[49,46]],[[49,12],[49,21]],["PLL"],["variable","wire"]],["sub_wire4",[[50,1],[50,38]],[[50,12],[50,21]],["PLL"],["variable","wire"]],["c0",[[51,1],[51,21]],[[51,7],[51,9]],["PLL"],["variable","wire"]],["altpll_component",[[53,1],[90,22]],[[53,8],[53,24]],["PLL"],["instance","altpll"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_VGA/top_tb.sv",[[[[[["tb",[[2,0],[2,12]],[[2,7],[2,9]],[],["module"]],[37,9]],[[["clk",[[3,1],[3,15]],[[3,5],[3,8]],["tb"],["variable","reg"]],["v_h_sync",[[5,1],[5,14]],[[5,6],[5,14]],["tb"],["variable","wire"]],["v_v_sync",[[6,1],[6,14]],[[6,6],[6,14]],["tb"],["variable","wire"]],["scan_pos_x",[[8,1],[8,23]],[[8,13],[8,23]],["tb"],["variable","wire"]],["scan_pos_y",[[9,1],[9,23]],[[9,13],[9,23]],["tb"],["variable","wire"]],["rgb",[[11,1],[11,15]],[[11,12],[11,15]],["tb"],["variable","wire"]],["VGA_Test_Screen_Inst",[[13,1],[18,2]],[[13,17],[13,37]],["tb"],["instance","VGA_Test_Screen"]],["VGA_Signal_Gen_Inst",[[20,1],[26,2]],[[20,16],[20,35]],["tb"],["instance","VGA_Signal_Gen"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_VGA/top.sv",[[[[[["top",[[0,0],[7,2]],[[0,7],[0,10]],[],["module"]],[44,9]],[[["clk12m",[[2,1],[2,19]],[[2,13],[2,19]],["top"],["port","logic"]],["gpio_d",[[4,1],[4,27]],[[4,21],[4,27]],["top"],["port","logic"]],["led",[[6,1],[6,23]],[[6,20],[6,23]],["top"],["port","logic"]],["pixel_clk",[[8,1],[8,15]],[[8,6],[8,15]],["top"],["variable","wire"]],["p_clk_pll",[[10,1],[10,34]],[[10,5],[10,14]],["top"],["instance","PLL"]],["rgb",[[12,1],[12,15]],[[12,12],[12,15]],["top"],["variable","wire"]],["hcounter",[[14,1],[14,20]],[[14,12],[14,20]],["top"],["variable","wire"]],["vcounter",[[15,1],[15,20]],[[15,12],[15,20]],["top"],["variable","wire"]],["hsync",[[17,1],[17,11]],[[17,6],[17,11]],["top"],["variable","wire"]],["vsync",[[18,1],[18,11]],[[18,6],[18,11]],["top"],["variable","wire"]],["VGA_Signal_Gen_Inst",[[20,1],[26,2]],[[20,16],[20,35]],["top"],["instance","VGA_Signal_Gen"]],["VGA_Test_Screen_Inst",[[28,1],[33,2]],[[28,17],[28,37]],["top"],["instance","VGA_Test_Screen"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_VGA/vga_controller.sv",[[[[[["VGA_Signal_Gen",[[0,0],[6,2]],[[0,7],[0,21]],[],["module"]],[33,9]],[[["pixel_clk",[[1,1],[1,21]],[[1,12],[1,21]],["VGA_Signal_Gen"],["port","wire"]],["hcounter",[[2,1],[2,26]],[[2,18],[2,26]],["VGA_Signal_Gen"],["port","reg"]],["vcounter",[[3,1],[3,26]],[[3,18],[3,26]],["VGA_Signal_Gen"],["port","reg"]],["hsync",[[4,1],[4,18]],[[4,13],[4,18]],["VGA_Signal_Gen"],["port","wire"]],["vsync",[[5,1],[5,18]],[[5,13],[5,18]],["VGA_Signal_Gen"],["port","wire"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max10_VGA/vga_test_screen.sv",[[[[[["VGA_Test_Screen",[[0,0],[5,2]],[[0,7],[0,22]],[],["module"]],[30,9]],[[["pixel_clk",[[1,1],[1,21]],[[1,12],[1,21]],["VGA_Test_Screen"],["port","wire"]],["x",[[2,1],[2,19]],[[2,18],[2,19]],["VGA_Test_Screen"],["port","reg"]],["y",[[3,1],[3,19]],[[3,18],[3,19]],["VGA_Test_Screen"],["port","reg"]],["rgb",[[4,1],[4,21]],[[4,18],[4,21]],["VGA_Test_Screen"],["port","reg"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Max1000 Template/top.sv",[[[[[["max1000_template",[[0,0],[36,2]],[[0,7],[0,23]],[],["module"]],[41,9]],[[["clk12m",[[2,1],[2,19]],[[2,13],[2,19]],["max1000_template"],["port","logic"]],["acc_sclk",[[5,1],[5,22]],[[5,14],[5,22]],["max1000_template"],["port","logic"]],["acc_mosi",[[6,1],[6,22]],[[6,14],[6,22]],["max1000_template"],["port","logic"]],["acc_miso",[[7,1],[7,22]],[[7,14],[7,22]],["max1000_template"],["port","logic"]],["acc_cs",[[8,1],[8,20]],[[8,14],[8,20]],["max1000_template"],["port","logic"]],["acc_int1",[[9,1],[9,22]],[[9,14],[9,22]],["max1000_template"],["port","logic"]],["acc_int2",[[10,1],[10,22]],[[10,14],[10,22]],["max1000_template"],["port","logic"]],["btn",[[13,1],[13,17]],[[13,14],[13,17]],["max1000_template"],["port","logic"]],["gpio_d",[[16,1],[16,27]],[[16,21],[16,27]],["max1000_template"],["port","logic"]],["gpio_a",[[17,1],[17,27]],[[17,21],[17,27]],["max1000_template"],["port","logic"]],["led",[[20,1],[20,24]],[[20,21],[20,24]],["max1000_template"],["port","logic"]],["pmod",[[23,1],[23,25]],[[23,21],[23,25]],["max1000_template"],["port","logic"]],["ram_clk",[[26,1],[26,28]],[[26,21],[26,28]],["max1000_template"],["port","logic"]],["ram_data",[[27,1],[27,29]],[[27,21],[27,29]],["max1000_template"],["port","logic"]],["ram_addr",[[28,1],[28,29]],[[28,21],[28,29]],["max1000_template"],["port","logic"]],["ram_dqm",[[29,1],[29,28]],[[29,21],[29,28]],["max1000_template"],["port","logic"]],["ram_bs",[[30,1],[30,27]],[[30,21],[30,27]],["max1000_template"],["port","logic"]],["ram_cke",[[31,1],[31,28]],[[31,21],[31,28]],["max1000_template"],["port","logic"]],["ram_ras",[[32,1],[32,28]],[[32,21],[32,28]],["max1000_template"],["port","logic"]],["ram_cas",[[33,1],[33,28]],[[33,21],[33,28]],["max1000_template"],["port","logic"]],["ram_we",[[34,1],[34,27]],[[34,21],[34,27]],["max1000_template"],["port","logic"]],["ram_cs",[[35,1],[35,27]],[[35,21],[35,27]],["max1000_template"],["port","logic"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Verilator_Tests/clk/top_tb.v",[[[[[["testbench",[[2,0],[2,17]],[[2,7],[2,16]],[],["module"]],[21,9]],[[["clk_25mhz",[[4,4],[4,21]],[[4,8],[4,17]],["testbench"],["variable","reg"]],["led",[[5,4],[5,18]],[[5,15],[5,18]],["testbench"],["variable","wire"]],["uut",[[7,4],[10,5]],[[7,8],[7,11]],["testbench"],["instance","top"]]]]]]],null,0]],["/home/benk/projects/fpga-basics/Verilator_Tests/clk/top.v",[[[[[["top",[[0,0],[3,2]],[[0,7],[0,10]],[],["module"]],[5,9]],[[["clk_25mhz",[[1,4],[1,19]],[[1,10],[1,19]],["top"],["port","input"]],["led",[[2,4],[2,20]],[[2,17],[2,20]],["top"],["port","output"]]]]]]],null,0]]]}
\ No newline at end of file
diff --git a/.nvim/svlangserver/linter.vc b/.nvim/svlangserver/linter.vc
new file mode 100644
index 0000000..26b7557
--- /dev/null
+++ b/.nvim/svlangserver/linter.vc
@@ -0,0 +1,8 @@
++incdir+/home/benk/projects/fpga-basics/Max10_RT
++incdir+/home/benk/projects/fpga-basics/Max10_VGA
++incdir+/home/benk/projects/fpga-basics/Max1000 Template
++incdir+/home/benk/projects/fpga-basics/Verilator_Tests/clk
++incdir+/home/benk/projects/fpga-basics/Max10_RT
++incdir+/home/benk/projects/fpga-basics/Max10_VGA
++incdir+/home/benk/projects/fpga-basics/Max1000 Template
++incdir+/home/benk/projects/fpga-basics/Verilator_Tests/clk
\ No newline at end of file
diff --git a/Verilator_Tests/clk/sim_main.cpp b/Verilator_Tests/clk/sim_main.cpp
new file mode 100644
index 0000000..24a5eb0
--- /dev/null
+++ b/Verilator_Tests/clk/sim_main.cpp
@@ -0,0 +1,29 @@
+#include "Vtop.h"
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+
+int main(int argc, char** argv) {
+    Verilated::commandArgs(argc, argv);
+    Verilated::traceEverOn(true);
+
+    Vtop* top = new Vtop;
+
+    VerilatedVcdC* tfp = new VerilatedVcdC;
+    top->trace(tfp, 99);
+    tfp->open("wave.vcd");
+
+    int clk = 0;
+    for (int time = 0; time < 500; time++) {
+        // Toggle clk every 20 time units (simulate 25 MHz)
+        if ((time % 20) == 0)
+            clk = !clk;
+
+        top->clk_25mhz = clk;
+        top->eval();
+        tfp->dump(time);
+    }
+
+    tfp->close();
+    delete top;
+    return 0;
+}
diff --git a/Verilator_Tests/clk/top_tb.v b/Verilator_Tests/clk/top_tb.v
new file mode 100644
index 0000000..9210f31
--- /dev/null
+++ b/Verilator_Tests/clk/top_tb.v
@@ -0,0 +1,22 @@
+`timescale 1ns / 1ps
+
+module top_tb;
+
+    reg clk_25mhz = 0;
+    wire [3:0] led;
+
+    top uut (
+        .clk_25mhz(clk_25mhz),
+        .led(led)
+    );
+
+    always #20 clk_25mhz = ~clk_25mhz;
+
+    initial begin
+        $dumpfile("top_tb.vcd");
+        $dumpvars(0, top_tb);
+
+        #500 $finish;
+    end
+
+endmodule
diff --git a/Verilator_Tests/clk/ulx4m.mk b/Verilator_Tests/clk/ulx4m.mk
index 2534bb0..966b943 100644
--- a/Verilator_Tests/clk/ulx4m.mk
+++ b/Verilator_Tests/clk/ulx4m.mk
@@ -1,10 +1,8 @@
 PIN_DEF ?= ./ulx4m_v002.lpf
-
 DEVICE ?= 85k
-
 BUILDDIR = bin
-
 TOP ?= top
+VERILOG ?= $(wildcard *.v)
 
 compile: $(BUILDDIR)/toplevel.bit
 
@@ -14,12 +12,27 @@ prog: $(BUILDDIR)/toplevel.bit
 dfu: $(BUILDDIR)/toplevel.bit
 	dfu-util -a 0 -D  $^ -R
 
+sim: $(BUILDDIR)/sim.out
+	$^
+
+$(BUILDDIR)/sim.out: $(VERILOG) sim_main.cpp
+	mkdir -p $(BUILDDIR)
+	verilator -Wall --cc $(VERILOG) \
+		--top-module top \
+		--exe sim_main.cpp \
+		--build -CFLAGS "-O2 -std=c++17" \
+		--trace \
+		--Wno-UNUSEDSIGNAL \
+		--Wno-UNDRIVEN \
+		--timing
+	cp obj_dir/Vtop $@
+
 $(BUILDDIR)/toplevel.json: $(VERILOG)
 	mkdir -p $(BUILDDIR)
 	yosys \
-	-p "read -sv $^" \
-	-p "hierarchy -top ${TOP}" \
-	-p "synth_ecp5 -abc9 -json $@" \
+		-p "read -sv $^" \
+		-p "hierarchy -top ${TOP}" \
+		-p "synth_ecp5 -abc9 -json $@" \
 
 $(BUILDDIR)/%.config: $(PIN_DEF) $(BUILDDIR)/toplevel.json
 	nextpnr-ecp5 --${DEVICE} --package CABGA381 --timing-allow-fail --freq 25 --textcfg  $@ --json $(filter-out $<,$^) --lpf $<
@@ -28,7 +41,7 @@ $(BUILDDIR)/toplevel.bit: $(BUILDDIR)/toplevel.config
 	ecppack --compress $^ $@
 
 clean:
-	rm -rf ${BUILDDIR}
+	rm -rf ${BUILDDIR} obj_dir
 
 .SECONDARY:
-.PHONY: compile clean prog
+.PHONY: compile clean prog dfu sim
diff --git a/Verilator_Tests/clk/wave.vcd b/Verilator_Tests/clk/wave.vcd
new file mode 100644
index 0000000..0bf4b40
--- /dev/null
+++ b/Verilator_Tests/clk/wave.vcd
@@ -0,0 +1,89 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module TOP $end
+  $var wire 1 # clk_25mhz $end
+  $var wire 4 $ led [3:0] $end
+  $scope module top $end
+   $var wire 1 # clk_25mhz $end
+   $var wire 4 $ led [3:0] $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+1#
+b0001 $
+#20
+0#
+b0000 $
+#40
+1#
+b0001 $
+#60
+0#
+b0000 $
+#80
+1#
+b0001 $
+#100
+0#
+b0000 $
+#120
+1#
+b0001 $
+#140
+0#
+b0000 $
+#160
+1#
+b0001 $
+#180
+0#
+b0000 $
+#200
+1#
+b0001 $
+#220
+0#
+b0000 $
+#240
+1#
+b0001 $
+#260
+0#
+b0000 $
+#280
+1#
+b0001 $
+#300
+0#
+b0000 $
+#320
+1#
+b0001 $
+#340
+0#
+b0000 $
+#360
+1#
+b0001 $
+#380
+0#
+b0000 $
+#400
+1#
+b0001 $
+#420
+0#
+b0000 $
+#440
+1#
+b0001 $
+#460
+0#
+b0000 $
+#480
+1#
+b0001 $
+#499