Files
fpga-basics/Max10_RT/raytracer.sv
Benjamin Kyd 279813aad7 that again
2022-06-06 21:20:05 +01:00

9 lines
119 B
Systemverilog

module Raytracer(
input wire pixel_clk,
input reg [10:0] x,
input reg [10:0] y,
output reg [2:0] rgb
);
endmodule