39 lines
599 B
Systemverilog
39 lines
599 B
Systemverilog
`timescale 1 ns / 100 ps
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module tb();
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reg clk = 1'b0;
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wire v_h_sync;
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wire v_v_sync;////////////////////////////////
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wire [10:0] scan_pos_x;
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wire [10:0] scan_pos_y;
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wire [2:0] rgb;
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VGA_Test_Screen VGA_Test_Screen_Inst(
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.pixel_clk(clk),
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.x(scan_pos_x),
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.y(scan_pos_y),
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.rgb(rgb)
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);
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VGA_Signal_Gen VGA_Signal_Gen_Inst(
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.pixel_clk(clk),
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.scan_x(scan_pos_x),
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.scan_y(scan_pos_y),
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.h_sync(v_h_sync),
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.v_sync(v_v_sync)
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);
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// 25MHz clock
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always #20 clk <= ~clk;
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initial begin
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$display($time, " Starting the Simulation");
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#1000
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$finish();
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end
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endmodule
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