24 lines
1.0 KiB
Plaintext
24 lines
1.0 KiB
Plaintext
Info: Start Nativelink Simulation process
|
|
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used
|
|
|
|
========= EDA Simulation Settings =====================
|
|
|
|
Sim Mode : RTL
|
|
Family : max10
|
|
Quartus root : c:/intelfpga_lite/21.1/quartus/bin64/
|
|
Quartus sim root : c:/intelfpga_lite/21.1/quartus/eda/sim_lib
|
|
Simulation Tool : questa intel fpga
|
|
Simulation Language : verilog
|
|
Simulation Mode : GUI
|
|
Sim Output File :
|
|
Sim SDF file :
|
|
Sim dir : simulation\modelsim
|
|
|
|
=======================================================
|
|
|
|
Info: Starting NativeLink simulation with Questa Intel FPGA software
|
|
Sourced NativeLink script c:/intelfpga_lite/21.1/quartus/common/tcl/internal/nativelink/modelsim.tcl
|
|
Warning: File Max10_VGA_run_msim_rtl_verilog.do already exists - backing up current file as Max10_VGA_run_msim_rtl_verilog.do.bak11
|
|
Info: Spawning Questa Intel FPGA Simulation software
|
|
Info: NativeLink simulation flow was successful
|