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fpga-basics/Max10_VGA/timings.sdc
Benjamin Kyd 94a37bd3c8 initial
2022-05-26 23:54:01 +01:00

9 lines
281 B
Tcl

# Clock constraints
create_clock -name "clk12m" -period 83.333ns [get_ports {clk12m}]
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty