32 lines
597 B
Systemverilog
32 lines
597 B
Systemverilog
module VGA_Test_Screen(
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input wire pixel_clk,
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input reg [10:0] x,
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input reg [10:0] y,
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output reg [2:0] rgb
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);
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always @ (posedge pixel_clk) begin
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if (x < 80 && y < 480)
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rgb <= 3'b111;
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else if (x < 160 && y < 480)
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rgb <= 3'b110;
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else if (x < 240 && y < 480)
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rgb <= 3'b101;
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else if (x < 320 && y < 480)
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rgb <= 3'b100;
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else if (x < 400 && y < 480)
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rgb <= 3'b011;
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else if (x < 480 && y < 480)
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rgb <= 3'b010;
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else if (x < 560 && y < 480)
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rgb <= 3'b001;
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else if (x < 640 && y < 480)
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rgb <= 3'b000;
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else
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rgb <= 3'b000;
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end
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endmodule
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