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fpga-basics
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fpga-basics
/
Verilator_Tests
/
clk
History
Ben Kyd
617f331c81
spi
2025-07-07 23:41:44 +01:00
..
Makefile
TEsting yosys
2025-07-07 12:11:19 +01:00
sim_main.cpp
epic testbenches
2025-07-07 15:48:53 +01:00
top_tb.v
spi
2025-07-07 23:41:44 +01:00
top.v
spi
2025-07-07 23:41:44 +01:00
ulx4m_v002.lpf
TEsting yosys
2025-07-07 12:11:19 +01:00
ulx4m.mk
testbenches
2025-07-07 15:19:09 +01:00
wave.vcd
spi
2025-07-07 23:41:44 +01:00