67 lines
4.1 KiB
Plaintext
67 lines
4.1 KiB
Plaintext
set_global_assignment -name FAMILY "MAX 10"
|
|
set_global_assignment -name DEVICE 10M08SAU169C8G
|
|
set_global_assignment -name TOP_LEVEL_ENTITY top
|
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
|
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:14:16 FEBRUARY 14, 2018"
|
|
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
|
|
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
|
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
|
|
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Precision Synthesis"
|
|
set_global_assignment -name EDA_LMF_FILE mentor.lmf -section_id eda_design_synthesis
|
|
set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis
|
|
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (SystemVerilog)"
|
|
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
|
|
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
|
|
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "Stamp (Timing)"
|
|
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT STAMP -section_id eda_board_design_timing
|
|
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "ViewDraw (Symbol)"
|
|
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VIEWDRAW -section_id eda_board_design_symbol
|
|
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "IBIS (Signal Integrity)"
|
|
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT IBIS -section_id eda_board_design_signal_integrity
|
|
set_global_assignment -name VCCA_USER_VOLTAGE 3.3V
|
|
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
|
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
|
|
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
|
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
|
|
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
|
|
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
|
|
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
|
|
|
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
|
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
|
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
|
|
|
|
|
# Pin assignments
|
|
set_location_assignment PIN_H6 -to clk12m
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk12m
|
|
|
|
|
|
# Clock assignment
|
|
|
|
|
|
|
|
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
|
|
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
|
|
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb -section_id eda_simulation
|
|
set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation
|
|
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb
|
|
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb -section_id tb
|
|
set_global_assignment -name EDA_TEST_BENCH_FILE top_tb.sv -section_id tb
|
|
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_acc.tcl
|
|
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_button.tcl
|
|
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_gpio.tcl
|
|
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_led.tcl
|
|
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_pmod.tcl
|
|
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_ram.tcl
|
|
set_global_assignment -name SDC_FILE timings.sdc
|
|
set_global_assignment -name QIP_FILE PLL.qip
|
|
set_global_assignment -name SYSTEMVERILOG_FILE top.sv
|
|
set_global_assignment -name SYSTEMVERILOG_FILE top_tb.sv
|
|
set_global_assignment -name SYSTEMVERILOG_FILE vga_controller.sv
|
|
set_global_assignment -name SYSTEMVERILOG_FILE vga_test_screen.sv
|
|
set_global_assignment -name SYSTEMVERILOG_FILE raytracer.sv
|
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |