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fpga-basics/Max10_RT/PLL.qip
Benjamin Kyd 279813aad7 that again
2022-06-06 21:20:05 +01:00

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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "21.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "PLL.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL.ppf"]