37 lines
592 B
Verilog
37 lines
592 B
Verilog
module top (
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input wire clk_25mhz,
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output wire spi_clk,
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output wire spi_mosi,
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input wire spi_miso,
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output wire spi_cs
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);
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// we would prefer fifo
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wire[7:0] miso;
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wire[7:0] mosi = 8'b01101011;
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reg busy = 0;
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reg start = 0;
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always @(posedge clk_25mhz) begin
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start <= 0;
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if (!busy && !start) begin
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start <= 1;
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end
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end
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spi_master spimaster0(
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.clk(clk_25mhz),
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.spi_clk(spi_clk),
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.start(start),
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.data_out(mosi),
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.spi_mosi(spi_mosi),
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.data_in(miso),
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.spi_miso(spi_miso),
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.busy(busy),
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.spi_cs(spi_cs)
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);
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endmodule
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