Files
fpga-basics/Max10_VGA/PLL.qip
Benjamin Kyd 94a37bd3c8 initial
2022-05-26 23:54:01 +01:00

8 lines
496 B
Plaintext

set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "21.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "PLL.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL.ppf"]