43 lines
825 B
Systemverilog
43 lines
825 B
Systemverilog
module max1000_template (
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// Main 12M clock
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input logic clk12m,
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// Accelerometer
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output logic acc_sclk,
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output logic acc_mosi,
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input logic acc_miso,
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output logic acc_cs,
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input logic acc_int1,
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input logic acc_int2,
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// Onboard button
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input logic btn,
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// Header GPIO
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inout logic [14:0] gpio_d,
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input logic [7:0] gpio_a,
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// Onboard LEDs
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output logic [8:1] led,
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// PMOD header
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inout logic [8:1] pmod,
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// Onboard RAM
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output logic ram_clk,
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inout logic [15:0] ram_data,
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output logic [13:0] ram_addr,
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output logic [1:0] ram_dqm,
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output logic [1:0] ram_bs,
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output logic ram_cke,
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output logic ram_ras,
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output logic ram_cas,
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output logic ram_we,
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output logic ram_cs
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);
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// This is the top module, enter your design here
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// Happy HDL :]
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endmodule
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