From 05e498e33588d274ff1bf8fa57553f09db78db4a Mon Sep 17 00:00:00 2001 From: Benjamin Kyd Date: Thu, 22 Jun 2023 01:11:24 +0100 Subject: [PATCH] This passes gorbit smh --- src/err.rs | 108 ++++++++++++++++++++++++++++++++++++++ src/ext/decode.rs | 128 ++++++++++++++++++++++++++++++++++++++++++---- src/main.rs | 1 + 3 files changed, 226 insertions(+), 11 deletions(-) create mode 100644 src/err.rs diff --git a/src/err.rs b/src/err.rs new file mode 100644 index 0000000..fe2c399 --- /dev/null +++ b/src/err.rs @@ -0,0 +1,108 @@ +// #[derive(Debug, Copy, Clone)] +// pub enum Trap { +// Exception(Exception), +// Interrupt(Interrupt), +// } +// +// #[derive(Debug, Eq, PartialEq, Copy, Clone)] +// pub enum Exception { +// FetchMisaligned(u64), +// LoadMisaligned(u64), +// StoreMisaligned(u64), +// // IllegalInsn(InsnT), +// FetchAccess(u64), +// LoadAccess(u64), +// StoreAccess(u64), +// FetchPageFault(u64), +// LoadPageFault(u64), +// StorePageFault(u64), +// Breakpoint, +// UCall, +// SCall, +// MCall, +// } +// impl From for Exception { +// fn from(e: Error) -> Self { +// Exception::IllegalInsn(e.ir()) +// } +// } +// impl Exception { +// pub const fn code(&self) -> RegT { +// match self { +// Exception::FetchMisaligned(_) => 0, +// Exception::FetchAccess(_) => 1, +// Exception::IllegalInsn(_) => 2, +// Exception::Breakpoint => 3, +// Exception::LoadMisaligned(_) => 4, +// Exception::LoadAccess(_) => 5, +// Exception::StoreMisaligned(_) => 6, +// Exception::StoreAccess(_) => 7, +// Exception::UCall => 8, +// Exception::SCall => 9, +// Exception::MCall => 11, +// Exception::FetchPageFault(_) => 12, +// Exception::LoadPageFault(_) => 13, +// Exception::StorePageFault(_) => 15, +// } +// } +// pub const fn tval(&self) -> RegT { +// match self { +// Exception::FetchMisaligned(addr) => *addr as RegT, +// Exception::FetchAccess(addr) => *addr as RegT, +// Exception::IllegalInsn(inst) => *inst as RegT, +// Exception::Breakpoint => 0 as RegT, +// Exception::LoadMisaligned(addr) => *addr as RegT, +// Exception::LoadAccess(addr) => *addr as RegT, +// Exception::StoreMisaligned(addr) => *addr as RegT, +// Exception::StoreAccess(addr) => *addr as RegT, +// Exception::UCall => 0 as RegT, +// Exception::SCall => 0 as RegT, +// Exception::MCall => 0 as RegT, +// Exception::FetchPageFault(addr) => *addr as RegT, +// Exception::LoadPageFault(addr) => *addr as RegT, +// Exception::StorePageFault(addr) => *addr as RegT, +// } +// } +// +// pub const fn executed(&self) -> bool { +// match self { +// Exception::Breakpoint => true, +// Exception::UCall => true, +// Exception::SCall => true, +// Exception::MCall => true, +// _ => false, +// } +// } +// } +// +// #[derive(Debug, Copy, Clone)] +// pub enum Interrupt { +// USInt, +// SSInt, +// MSInt, +// UTInt, +// STInt, +// MTInt, +// UEInt, +// SEInt, +// MEInt, +// } +// +// impl Interrupt { +// pub const fn code(&self) -> RegT { +// match self { +// Interrupt::USInt => 0, +// Interrupt::SSInt => 1, +// Interrupt::MSInt => 3, +// Interrupt::UTInt => 4, +// Interrupt::STInt => 5, +// Interrupt::MTInt => 7, +// Interrupt::UEInt => 8, +// Interrupt::SEInt => 9, +// Interrupt::MEInt => 11, +// } +// } +// pub const fn tval(&self) -> RegT { +// 0 +// } +// } diff --git a/src/ext/decode.rs b/src/ext/decode.rs index 221aed2..ceb4438 100644 --- a/src/ext/decode.rs +++ b/src/ext/decode.rs @@ -1,16 +1,100 @@ +use modular_bitfield::prelude::*; use bits::match_mask; use crate::system::rv32; use crate::cpu; +// trait Instruction { +// fn impl_register(&self, exts: &mut Vec, name: &'static str) { +// for ext in exts { +// if ext.name == name { +// exts.add(self) +// } +// } +// } +// } +// +// fn main() { +// let mut extensions = vec![ext1, ext2, ...]; +// ADDI.register(&extensions); +// SUBI.register(&extensions); +// } +// +// // ... +// +// impl Instruction for ADDI { +// fn register(&self, exts: &mut Vec) { +// self.impl_register(exts, "instr_set") +// } +// } + +// Null undecided type +#[bitfield] +#[derive(Debug)] +pub struct NullType { + pub opcode: B7, + pub _undefined: B25, +} + +// Arithmetic logic +#[bitfield] +#[derive(Debug)] +pub struct RType { + pub opcode: B7, + pub rd: B5, + pub funct3: B3, + pub rs1: B5, + pub rs2: B5, + pub funct7: B7, +} + +// Loads & immeiate arithmetic +#[bitfield] +#[derive(Debug)] +pub struct IType { + pub opcode: B7, + pub rd: B5, + pub funct3: B3, + pub rs1: B5, + pub imm: B12, +} + + +enum EncodingType { + R(RType), + I(IType), +} + +#[repr(align(8))] +pub union GenInstruction { + pub inst: rv32::Word, + pub null: std::mem::ManuallyDrop, + pub R: std::mem::ManuallyDrop, + pub I: std::mem::ManuallyDrop, +} + trait Instruction { - fn match_inst(inst: rv32::Word) -> bool; + fn register(&self, ext: &mut Extension) where Self: Sized { + ext.register(Box::new(self)); + } + fn decode(&self); + fn match_inst(&self, inst: rv32::Word) -> bool; fn step(&self, inst: rv32::Word, state: &mut cpu::CPU); } +#[derive(Copy, Clone)] struct ADDI; +impl ADDI { + fn new() -> ADDI { + ADDI + } +} impl Instruction for ADDI { - fn match_inst(inst: rv32::Word) -> bool { + fn decode(&self) { + + } + + fn match_inst(&self, inst: rv32::Word) -> bool { match_mask!(inst, "xxxxxxxxxxxxxxxxxx000xxxx0010011") } @@ -19,17 +103,39 @@ impl Instruction for ADDI { } -#[derive(Clone, Copy)] -enum I { - ADDI(ADDI), +trait GenExtension { + fn register(&mut self, inst: Box) { + } } -#[derive(Clone, Copy)] -enum Extensions { - I, +struct Extension { + instruction_set: Vec>, } -pub fn decode_inst(inst: rv32::Word) -> fn() { - // we need to go over every instruction and see if it matches - // we can do smarter things with cacheing later - this aint blazin +impl GenExtension for Extension { + } + +impl Extension { + fn new() -> Extension { + Extension { + instruction_set: Vec::new(), + } + } +} + +struct ExtensionI; +impl GenExtension for ExtensionI { + +} + +pub fn load_extensions(ext: Vec) { + for extension in ext { + + } +} + +// pub fn decode_inst(inst: rv32::Word) -> fn() { +// // we need to go over every instruction and see if it matches +// // we can do smarter things with cacheing later - this aint blazin +// } diff --git a/src/main.rs b/src/main.rs index 53a63fb..fa6ca77 100644 --- a/src/main.rs +++ b/src/main.rs @@ -5,6 +5,7 @@ use std::{cell::RefCell, rc::Rc}; mod cpu; mod ext; +mod err; mod system; mod inst;