Ok this is epic

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "riscv-gnu-toolchain"]
+	path = riscv-gnu-toolchain
+	url = https://github.com/riscv/riscv-gnu-toolchain

src/main.rs

@@ -1,10 +1,18 @@
+use std::io::Read;
+use std::io::BufReader;
+use std::fs::File;
+
 const XLEN: usize = 32;
+
+const DRAM_SIZE: usize = 1 * 1024 * 1024 * 1024; // 1GB
+const DRAM_BASE: usize = 0x800000000;
+
 // define words as byte fraction
-const QUADWORD: usize = 16;
-const DOUBLEWORD: usize = 8;
-const WORD: usize = 4;
-const HALFWORD: usize = 2;
-const BYTE: usize = 1;
+//const QUADWORD: usize = 16;
+//const DOUBLEWORD: usize = 8;
+//const WORD: usize = 4;
+//const HALFWORD: usize = 2;
+//const BYTE: usize = 1;
 
 type QuadWord = u128;
 type DoubleWord = u64;
@@ -12,18 +20,84 @@ type Word = u32;
 type HalfWord = u16;
 type Byte = u8;
 
+struct Bus {
+    // 1GB of memory
+    memory: Vec<Byte>,
+}
+
+impl Bus {
+    fn new() -> Bus {
+        Bus {
+            memory: vec![0; DRAM_SIZE],
+        }
+    }
+}
+
+impl Default for Bus {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+struct Instruction {
+    opcode: u8,
+    rd: u8,
+    rs1: u8,
+    rs2: u8,
+    funct3: u8,
+    funct7: u8,
+    imm: u32,
+}
+
 struct VMRV32I {
+    // 32 bi bus
+    bus: Bus,
     // 32 registers
     x: [Word; 32],
     // 32-bit program counter
     pc: Word,
 }
 
-struct VMChunk {
+impl VMRV32I {
+    fn new() -> VMRV32I {
+        VMRV32I {
+            bus: Bus::new(),
+            x: [0; 32],
+            pc: 0,
+        }
+    }
 
+    fn load_prog(&mut self, file: &str) {
+        println!("VM > Loading program: {}", file);
+
+        let f = File::open(file).expect("file not found");
+        let mut reader = BufReader::new(f);
+        let mut buffer = Vec::new();
+        reader.read_to_end(&mut buffer).expect("error reading file");
+
+        print!("VM > Program size: {} bytes", buffer.len());
+        // put program at the base of DRAM
+        for i in 0..buffer.len() {
+            self.bus.memory[i + DRAM_BASE] = buffer[i];
+        }
+
+        println!("VM > Program loaded to 0x{:08x}", self.pc);
+    }
+
+    fn init_cpu(&mut self) {
+        println!("VM RISC-V 32I CPU");
+        println!("-----------------");
+        println!("VM > Initializing CPU");
+
+        self.pc = DRAM_BASE as Word;
+        self.x[0] = 0; // x0 is tied to ground
+    }
 }
 
 fn main() {
-    println!("Hello, world!");
-}
+    println!("VM Starting Up");
 
+    let mut cpu = VMRV32I::new();
+    cpu.load_prog("test.bin");
+    cpu.init_cpu();
+}

test/Makefile

@@ -0,0 +1,18 @@
+GCC_COMPILER=riscv32-unknown-elf-gcc
+GCC_OBJCOPY=riscv32-unknown-elf-objcopy
+
+all:
+	assemble
+	build
+	@echo "Done"
+
+assemble:
+	$(GCC_COMPILER) -S test.c
+
+build:
+	$(GCC_COMPILER) -Wl,-Ttext=0x0 -nostdlib -march=rv64i -mabi=lp64 -o test test.S
+	$(GCC_OBJCOPY) -O binary test test.bin
+
+clean:
+	rm -f test test.bin
+

test/basic.S

@@ -0,0 +1,6 @@
+ADDI x2, x0, 1
+
+loop:
+   SUB x1, x1, x2
+   SW  x1, 4(x0) 
+   BLT x0, x1, loop

test/test.S

@@ -0,0 +1,6 @@
+ADDI x2, x0, 1
+
+loop:
+   SUB x1, x1, x2
+   SW  x1, 4(x0) 
+   BLT x0, x1, loop

test/test.c

@@ -0,0 +1,4 @@
+int main() {
+    int x = 1 + 2;
+    return 0;
+}