From 59dcf80fbed05ac4bf88bbaf3095e56edbb81e1b Mon Sep 17 00:00:00 2001
From: Benjamin Kyd <benjamin.kyd@intel.com>
Date: Fri, 2 Jun 2023 01:17:22 +0100
Subject: [PATCH] seperating the ISA from the extension

---
 src/ext/i/mod.rs | 3 +++
 src/main.rs      | 7 ++-----
 2 files changed, 5 insertions(+), 5 deletions(-)
 create mode 100644 src/ext/i/mod.rs

diff --git a/src/ext/i/mod.rs b/src/ext/i/mod.rs
new file mode 100644
index 0000000..b28b04f
--- /dev/null
+++ b/src/ext/i/mod.rs
@@ -0,0 +1,3 @@
+
+
+
diff --git a/src/main.rs b/src/main.rs
index 15b4fa8..8f922ed 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -10,7 +10,7 @@ mod rv32;
 use crate::bus::*;
 
 // Register ABI         Description             Saver
-// x0       zero        Zero                    constant —
+// x0       zero        Zero                    Immutable
 // x1       ra          Return address          Callee
 // x2       sp          Stack pointer           Callee
 // x3       gp          Global pointer          —
@@ -24,11 +24,8 @@ use crate::bus::*;
 // x18-x27  s2-s11      Saved registers         Callee
 // x28-x31  t3-t6       Temporaries             Caller
 struct VMRV32I {
-    // 32 bi bus
     bus: bus::Bus,
-    // 32 registers
     x: [rv32::Word; 32],
-    // 32-bit program counter
     pc: rv32::Word,
 }
 
@@ -100,7 +97,7 @@ impl VMRV32I {
     }
 
     fn exec(&mut self) {
-        while self.pc > ram::DRAM_SIZE as u32 {
+        while self.pc - bus::DRAM_BASE < ram::DRAM_SIZE as u32 {
             // fetch
             let inst = self.fetch();
             println!("VM > Fetched 0x{:08x}: 0x{:08x}", self.pc, unsafe {