203 lines
4.6 KiB
ArmAsm
203 lines
4.6 KiB
ArmAsm
.global _start
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_start: # Clear out two registers
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xor x1, x1, x1
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xor x2, x2, x2
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# Set x1 to one
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addi x1, x1, 1
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# Test resgister+register adds.
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add x2, x1, x1
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add x2, x2, x1
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add x2, x1, x2
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# test LUI
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lui x2, 0xFFFFF
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# test immediate shifts
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srai x2,x2,2
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srli x2,x2,4
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slli x2,x2,2
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# test AUIPC
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AUIPC x2, 0x12345
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#######################################
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# Testing different size stores
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#######################################
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# Load the RAM address into x7
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lui x7, 0x10000
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# Test four x byte stores
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sb x2, 0(x7)
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sb x2, 1(x7)
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sb x2, 2(x7)
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sb x2, 3(x7)
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# Load them back as a word
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lw x3, 0(x7)
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# Test two x halfword stores
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sh x2, 0(x7)
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sh x2, 2(x7)
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# Load them back as a word
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lw x3, 0(x7)
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#Create a new test value 0x89ABCDEF
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lui x2, 0x89ABD
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addi x2, x2, 0xFFFFFDEF
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# Store it into RAM
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sw x2, 0(x7)
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# Load them back as a word
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lw x3, 0(x7)
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# Test signed halfword loads
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lh x2, 0(x7)
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lh x2, 2(x7)
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# Test signed byte loads
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lb x2, 0(x7)
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lb x2, 1(x7)
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lb x2, 2(x7)
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lb x2, 3(x7)
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# Test unsigned halfword loads
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lhu x2, 0(x7)
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lhu x2, 2(x7)
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# Test unsigned byte loads
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lbu x2, 0(x7)
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lbu x2, 1(x7)
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lbu x2, 2(x7)
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lbu x2, 3(x7)
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# Setup for reg <= reg op reg instructions
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lui x2, 0x66666
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addi x2, x2, 0x666
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lui x3, 0xCCCCD
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addi x3, x3, 0xFFFFFCCC
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# reg <= reg op reg instructions
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add x4, x2, x3
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add x4, x3, x2
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sub x4, x2, x3
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sub x4, x3, x2
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sll x4, x2, x3
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sll x4, x3, x2
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slt x4, x2, x3
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slt x4, x3, x2
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sltu x4, x2, x3
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sltu x4, x3, x2
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xor x4, x2, x3
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xor x4, x3, x2
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srl x4, x2, x3
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srl x4, x3, x2
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sra x4, x2, x3
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sra x4, x3, x2
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or x4, x2, x3
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or x4, x3, x2
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and x4, x2, x3
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and x4, x3, x2
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# reg <= reg op immediate instructions
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addi x4, x3, 0x666
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slti x4, x3, 0x666
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sltiu x4, x3, 0x666
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xori x4, x3, 0x666
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ori x4, x3, 0x666
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andi x4, x3, 0x666
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slli x4, x3, 6
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srli x4, x3, 6
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srai x4, x3, 6
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# empty out x3 and test relative jump
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andi x3, x0, 0
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jal x4, tmp0
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ori x3, x3, 1
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tmp0: ori x3, x3, 2
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ori x3, x3, 4
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# Testing conditional branckes
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xor x2, x2, x2
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addi x3, x2, 0x8
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addi x4, x2, 0x8
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# Test conditionals with rboth registers = 0x8
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beq x3, x4, tmp1
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ori x2, x2, 1
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tmp1: bne x3, x4, tmp2
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ori x2, x2, 2
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tmp2: blt x3, x4, tmp3
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ori x2, x2, 4
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tmp3: bge x3, x4, tmp4
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ori x2, x2, 8
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tmp4: bltu x3, x4, tmp5
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ori x2, x2, 0x10
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tmp5: bgeu x3, x4, tmp6
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ori x2, x2, 0x20
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tmp6:
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# Set up for next pass of conditionals
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xor x2, x2, x2
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addi x4, x3, 8
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beq x3, x4, tmp11
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ori x2, x2, 0x01
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tmp11: bne x3, x4, tmp12
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ori x2, x2, 0x02
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tmp12: blt x3, x4, tmp13
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ori x2, x2, 0x04
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tmp13: bge x3, x4, tmp14
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ori x2, x2, 0x08
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tmp14: bltu x3, x4, tmp15
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ori x2, x2, 0x10
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tmp15: bgeu x3, x4, tmp16
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ori x2, x2, 0x20
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tmp16:
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# Set up for next pass of conditionals
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xor x2, x2, x2
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addi x4, x2, 0xFFFFFFE0
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beq x3, x4, tmp21
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ori x2, x2, 0x01
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tmp21: bne x3, x4, tmp22
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ori x2, x2, 0x02
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tmp22: blt x3, x4, tmp23
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ori x2, x2, 0x04
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tmp23: bge x3, x4, tmp24
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ori x2, x2, 0x08
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tmp24: bltu x3, x4, tmp25
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ori x2, x2, 0x10
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tmp25: bgeu x3, x4, tmp26
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ori x2, x2, 0x20
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tmp26:
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# Now testing the CRS instructions
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csrrs x5, mvendorid, x0
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csrrs x5, marchid, x0
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csrrs x5, mimpid, x0
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csrrs x5, mhartid, x0
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# Set up the trap vector
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lui x2, 0xF0000
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ori x2, x2, 0x200
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csrrw x2, mtvec, x2
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ori x2, x2, 0x200 # Allow the testing of last instruction
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.word 0xFFF0007E # An invalid instruction
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.word 0
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.word 0
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traptarget:
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# Target for the "illegal opcode" vector
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csrrw x5, mcause, x0
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csrrw x5, mepc, x0
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# Padding
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addi x1, x1, 1
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addi x1, x1, 1
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addi x1, x1, 1
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addi x1, x1, 1
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addi x1, x1, 1
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addi x1, x1, 1
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addi x1, x1, 1
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.data
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.word 0
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.end
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