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This commit is contained in:
Benjamin Kyd
2022-05-31 00:25:12 +01:00
parent 0ade47e196
commit 8d65a966cb
10 changed files with 135 additions and 22 deletions
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1
Max10_VGA/Max10_VGA.qsf
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@@ -62,4 +62,5 @@ set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb -section_id tb
set_global_assignment -name EDA_TEST_BENCH_FILE top_tb.sv -section_id tb
set_global_assignment -name SYSTEMVERILOG_FILE vga_test_screen.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Max10_VGA/Max10_VGA.qws
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12
Max10_VGA/PLL.v
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@@ -91,9 +91,9 @@ module PLL (
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 480,
altpll_component.clk0_divide_by = 12,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1007,
altpll_component.clk0_multiply_by = 25,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 83333,
@@ -169,7 +169,7 @@ endmodule
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.174999"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -194,7 +194,7 @@ endmodule
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.17500000"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
@@ -237,9 +237,9 @@ endmodule
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "480"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1007"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333"

8
Max10_VGA/PLL_bb.v
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@@ -62,7 +62,7 @@ endmodule
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.174999"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -87,7 +87,7 @@ endmodule
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.17500000"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
@@ -130,9 +130,9 @@ endmodule
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "480"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1007"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333"

58
Max10_VGA/greybox_tmp/cbx_args.txt Normal file
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@@ -0,0 +1,58 @@
BANDWIDTH_TYPE=AUTO
CLK0_DIVIDE_BY=12
CLK0_DUTY_CYCLE=50
CLK0_MULTIPLY_BY=25
CLK0_PHASE_SHIFT=0
COMPENSATE_CLOCK=CLK0
INCLK0_INPUT_FREQUENCY=83333
INTENDED_DEVICE_FAMILY="MAX 10"
LPM_TYPE=altpll
OPERATION_MODE=NORMAL
PLL_TYPE=AUTO
PORT_ACTIVECLOCK=PORT_UNUSED
PORT_ARESET=PORT_UNUSED
PORT_CLKBAD0=PORT_UNUSED
PORT_CLKBAD1=PORT_UNUSED
PORT_CLKLOSS=PORT_UNUSED
PORT_CLKSWITCH=PORT_UNUSED
PORT_CONFIGUPDATE=PORT_UNUSED
PORT_FBIN=PORT_UNUSED
PORT_INCLK0=PORT_USED
PORT_INCLK1=PORT_UNUSED
PORT_LOCKED=PORT_UNUSED
PORT_PFDENA=PORT_UNUSED
PORT_PHASECOUNTERSELECT=PORT_UNUSED
PORT_PHASEDONE=PORT_UNUSED
PORT_PHASESTEP=PORT_UNUSED
PORT_PHASEUPDOWN=PORT_UNUSED
PORT_PLLENA=PORT_UNUSED
PORT_SCANACLR=PORT_UNUSED
PORT_SCANCLK=PORT_UNUSED
PORT_SCANCLKENA=PORT_UNUSED
PORT_SCANDATA=PORT_UNUSED
PORT_SCANDATAOUT=PORT_UNUSED
PORT_SCANDONE=PORT_UNUSED
PORT_SCANREAD=PORT_UNUSED
PORT_SCANWRITE=PORT_UNUSED
PORT_clk0=PORT_USED
PORT_clk1=PORT_UNUSED
PORT_clk2=PORT_UNUSED
PORT_clk3=PORT_UNUSED
PORT_clk4=PORT_UNUSED
PORT_clk5=PORT_UNUSED
PORT_clkena0=PORT_UNUSED
PORT_clkena1=PORT_UNUSED
PORT_clkena2=PORT_UNUSED
PORT_clkena3=PORT_UNUSED
PORT_clkena4=PORT_UNUSED
PORT_clkena5=PORT_UNUSED
PORT_extclk0=PORT_UNUSED
PORT_extclk1=PORT_UNUSED
PORT_extclk2=PORT_UNUSED
PORT_extclk3=PORT_UNUSED
WIDTH_CLOCK=5
DEVICE_FAMILY="MAX 10"
CBX_AUTO_BLACKBOX=ALL
inclk
inclk
clk

29
Max10_VGA/top.sv
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@@ -12,13 +12,34 @@ module top (
wire vsync_pulse, hsync_pulse;
VGA_Controller controller(
wire [10:0] scan_pos_x;
wire [10:0] scan_pos_y;
wire [2:0] rgb;
VGA_Signal_Gen VGA_Signal_Gen_Inst(
.pixel_clk(pixel_clk),
.scan_x(scan_pos_x),
.scan_y(scan_pos_y),
.h_sync(hsync_pulse),
.v_sync(vsync_pulse)
);
VGA_Test_Screen VGA_Test_Screen_Inst(
.pixel_clk(pixel_clk),
.x(scan_pos_x),
.y(scan_pos_y),
.rgb(rgb)
);
assign gpio_d[14] = hsync_pulse;
assign gpio_d[13] = vsync_pulse;
assign gpio_d[11:9] = rgb;
// OopSS, need a fake ground pin here
assign gpio_d[6] = 0;
assign v_sync = gpio_d[12];
assign h_sync = gpio_d[13];
assign led[1] = 1;
endmodule

20
Max10_VGA/top_tb.sv
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@@ -6,14 +6,28 @@ module tb();
wire v_h_sync;
wire v_v_sync;
VGA_Controller VGA_Controller_Inst(
wire [10:0] scan_pos_x;
wire [10:0] scan_pos_y;
wire [2:0] rgb;
VGA_Signal_Gen VGA_Signal_Gen_Inst(
.pixel_clk(clk),
.scan_x(scan_pos_x),
.scan_y(scan_pos_y),
.h_sync(v_h_sync),
.v_sync(v_v_sync)
);
VGA_Test_Screen VGA_Test_Screen_Inst(
.pixel_clk(clk),
.x(scan_pos_x),
.y(scan_pos_y),
.rgb(rgb)
);
// 25MHz clock
always #5 clk <= ~clk;
always #20 clk <= ~clk;
initial begin
$display($time, " Starting the Simulation");

12
Max10_VGA/vga_controller.sv
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@@ -1,5 +1,7 @@
module VGA_Controller(
module VGA_Signal_Gen(
input wire pixel_clk,
output wire [10:0] scan_x,
output wire [10:0] scan_y,
output wire h_sync,
output wire v_sync
);
@@ -10,14 +12,14 @@ module VGA_Controller(
// VGA 640 x 480 @ 60 Hz
// pixel_clk 25.175MHz
always @(posedge pixel_clk) begin
if (h_counter < 799) begin
if (h_counter <= 800) begin
h_counter <= h_counter + 1;
end else begin
// reset scanline
h_counter <= 1'b0;
// step v_counter after hline
if (v_counter < 524) begin
if (v_counter <= 525) begin
v_counter <= v_counter + 1;
end else begin
v_counter <= 1'b0;
@@ -26,7 +28,7 @@ module VGA_Controller(
end
// generate sync pulses
assign h_sync = (h_counter < 96) ? 1'b1 : 1'b0;
assign v_sync = (v_counter < 2) ? 1'b1 : 1'b0;
assign h_sync = ~(h_counter <= 96);
assign v_sync = ~(v_counter <= 2);
endmodule

12
Max10_VGA/vga_test_screen.sv Normal file
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@@ -0,0 +1,12 @@
module VGA_Test_Screen(
input wire pixel_clk,
input wire [10:0] x,
input wire [10:0] y,
output wire [2:0] rgb
);
always @(posedge pixel_clk) begin
rgb[2:2] = 1;
end
endmodule

5
Max10_VGA/vga_test_screen.sv.bak Normal file
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@@ -0,0 +1,5 @@
VGA_Test_Screen(
input wire [10:0] scan_pos_x,
input wire [10:0] scan_pos_y,
output wire [2:0] rgb,
);