testbenches

Verilator_Tests/clk/sim_main.cpp

@@ -0,0 +1,29 @@
+#include "Vtop.h"
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+
+int main(int argc, char** argv) {
+    Verilated::commandArgs(argc, argv);
+    Verilated::traceEverOn(true);
+
+    Vtop* top = new Vtop;
+
+    VerilatedVcdC* tfp = new VerilatedVcdC;
+    top->trace(tfp, 99);
+    tfp->open("wave.vcd");
+
+    int clk = 0;
+    for (int time = 0; time < 500; time++) {
+        // Toggle clk every 20 time units (simulate 25 MHz)
+        if ((time % 20) == 0)
+            clk = !clk;
+
+        top->clk_25mhz = clk;
+        top->eval();
+        tfp->dump(time);
+    }
+
+    tfp->close();
+    delete top;
+    return 0;
+}

Verilator_Tests/clk/top_tb.v

@@ -0,0 +1,22 @@
+`timescale 1ns / 1ps
+
+module top_tb;
+
+    reg clk_25mhz = 0;
+    wire [3:0] led;
+
+    top uut (
+        .clk_25mhz(clk_25mhz),
+        .led(led)
+    );
+
+    always #20 clk_25mhz = ~clk_25mhz;
+
+    initial begin
+        $dumpfile("top_tb.vcd");
+        $dumpvars(0, top_tb);
+
+        #500 $finish;
+    end
+
+endmodule

Verilator_Tests/clk/ulx4m.mk

@@ -1,10 +1,8 @@
 PIN_DEF ?= ./ulx4m_v002.lpf
-
 DEVICE ?= 85k
-
 BUILDDIR = bin
-
 TOP ?= top
+VERILOG ?= $(wildcard *.v)
 
 compile: $(BUILDDIR)/toplevel.bit
 
@@ -14,12 +12,27 @@ prog: $(BUILDDIR)/toplevel.bit
 dfu: $(BUILDDIR)/toplevel.bit
 	dfu-util -a 0 -D  $^ -R
 
+sim: $(BUILDDIR)/sim.out
+	$^
+
+$(BUILDDIR)/sim.out: $(VERILOG) sim_main.cpp
+	mkdir -p $(BUILDDIR)
+	verilator -Wall --cc $(VERILOG) \
+		--top-module top \
+		--exe sim_main.cpp \
+		--build -CFLAGS "-O2 -std=c++17" \
+		--trace \
+		--Wno-UNUSEDSIGNAL \
+		--Wno-UNDRIVEN \
+		--timing
+	cp obj_dir/Vtop $@
+
 $(BUILDDIR)/toplevel.json: $(VERILOG)
 	mkdir -p $(BUILDDIR)
 	yosys \
-	-p "read -sv $^" \
-	-p "hierarchy -top ${TOP}" \
-	-p "synth_ecp5 -abc9 -json $@" \
+		-p "read -sv $^" \
+		-p "hierarchy -top ${TOP}" \
+		-p "synth_ecp5 -abc9 -json $@" \
 
 $(BUILDDIR)/%.config: $(PIN_DEF) $(BUILDDIR)/toplevel.json
 	nextpnr-ecp5 --${DEVICE} --package CABGA381 --timing-allow-fail --freq 25 --textcfg  $@ --json $(filter-out $<,$^) --lpf $<
@@ -28,7 +41,7 @@ $(BUILDDIR)/toplevel.bit: $(BUILDDIR)/toplevel.config
 	ecppack --compress $^ $@
 
 clean:
-	rm -rf ${BUILDDIR}
+	rm -rf ${BUILDDIR} obj_dir
 
 .SECONDARY:
-.PHONY: compile clean prog
+.PHONY: compile clean prog dfu sim

Verilator_Tests/clk/wave.vcd

@@ -0,0 +1,89 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module TOP $end
+  $var wire 1 # clk_25mhz $end
+  $var wire 4 $ led [3:0] $end
+  $scope module top $end
+   $var wire 1 # clk_25mhz $end
+   $var wire 4 $ led [3:0] $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+1#
+b0001 $
+#20
+0#
+b0000 $
+#40
+1#
+b0001 $
+#60
+0#
+b0000 $
+#80
+1#
+b0001 $
+#100
+0#
+b0000 $
+#120
+1#
+b0001 $
+#140
+0#
+b0000 $
+#160
+1#
+b0001 $
+#180
+0#
+b0000 $
+#200
+1#
+b0001 $
+#220
+0#
+b0000 $
+#240
+1#
+b0001 $
+#260
+0#
+b0000 $
+#280
+1#
+b0001 $
+#300
+0#
+b0000 $
+#320
+1#
+b0001 $
+#340
+0#
+b0000 $
+#360
+1#
+b0001 $
+#380
+0#
+b0000 $
+#400
+1#
+b0001 $
+#420
+0#
+b0000 $
+#440
+1#
+b0001 $
+#460
+0#
+b0000 $
+#480
+1#
+b0001 $
+#499