35 lines
553 B
Systemverilog
35 lines
553 B
Systemverilog
module VGA_Signal_Gen(
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input wire pixel_clk,
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output reg [9:0] hcounter,
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output reg [9:0] vcounter,
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output wire hsync,
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output wire vsync
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);
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always @(posedge pixel_clk) begin
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if(hcounter == 799) begin
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hcounter <= 0;
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if(vcounter == 524)
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vcounter <= 0;
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else
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vcounter <= vcounter + 1'b1;
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end
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else
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hcounter <= hcounter + 1'b1;
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if (vcounter >= 490 && vcounter < 492)
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vsync <= 1'b0;
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else
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vsync <= 1'b1;
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if (hcounter >= 656 && hcounter < 752)
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hsync <= 1'b0;
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else
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hsync <= 1'b1;
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end
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endmodule
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