25 lines
325 B
Systemverilog
25 lines
325 B
Systemverilog
`timescale 1 ns / 100 ps
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module tb();
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reg clk = 1'b0;
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reg [14:0] v_gpio_d;
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reg [8:1] v_led;
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VGA_Controller VGA_Controller_Inst(
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.pixel_clk(clk),
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.gpio_d(v_gpio_d)
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);
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// 25MHz clock
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always #5 clk <= ~clk;
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initial begin
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$display($time, " Starting the Simulation");
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#1000
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$finish();
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end
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endmodule
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