33 lines
636 B
Systemverilog
33 lines
636 B
Systemverilog
module VGA_Controller(
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input wire pixel_clk,
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output wire h_sync,
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output wire v_sync
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);
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reg [9:0] h_counter;
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reg [9:0] v_counter;
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// VGA 640 x 480 @ 60 Hz
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// pixel_clk 25.175MHz
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always @(posedge pixel_clk) begin
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if (h_counter < 799) begin
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h_counter <= h_counter + 1;
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end else begin
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// reset scanline
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h_counter <= 1'b0;
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// step v_counter after hline
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if (v_counter < 524) begin
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v_counter <= v_counter + 1;
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end else begin
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v_counter <= 1'b0;
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end
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end
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end
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// generate sync pulses
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assign h_sync = (h_counter < 96) ? 1'b1 : 1'b0;
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assign v_sync = (v_counter < 2) ? 1'b1 : 1'b0;
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endmodule
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