28 lines
485 B
Verilog
28 lines
485 B
Verilog
// Copyright 2025 Benjamin Kyd, All Rights Reserved
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`timescale 1ns / 1ps
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module top_tb;
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reg clk_25mhz = 0;
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reg spi_clk, spi_mosi, spi_miso, spi_cs;
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top uut (
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.clk_25mhz(clk_25mhz),
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.spi_clk(spi_clk),
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.spi_mosi(spi_mosi),
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.spi_miso(spi_miso),
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.spi_cs(spi_cs)
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);
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always #20 clk_25mhz = ~clk_25mhz;
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initial begin
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$dumpfile("top_tb.vcd");
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$dumpvars(0, top_tb);
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#500 $finish;
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end
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endmodule
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