48 lines
1.0 KiB
Makefile
48 lines
1.0 KiB
Makefile
PIN_DEF ?= ./ulx4m_v002.lpf
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DEVICE ?= 85k
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BUILDDIR = bin
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TOP ?= top
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VERILOG ?= $(wildcard *.v)
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compile: $(BUILDDIR)/toplevel.bit
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prog: $(BUILDDIR)/toplevel.bit
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fujprog $^
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dfu: $(BUILDDIR)/toplevel.bit
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dfu-util -a 0 -D $^ -R
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sim: $(BUILDDIR)/sim.out
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$^
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$(BUILDDIR)/sim.out: $(VERILOG) sim_main.cpp
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mkdir -p $(BUILDDIR)
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verilator -Wall --cc $(VERILOG) \
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--top-module top \
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--exe sim_main.cpp \
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--build -CFLAGS "-O2 -std=c++17" \
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--trace \
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--Wno-UNUSEDSIGNAL \
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--Wno-UNDRIVEN \
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--timing
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cp obj_dir/Vtop $@
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$(BUILDDIR)/toplevel.json: $(VERILOG)
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mkdir -p $(BUILDDIR)
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yosys \
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-p "read -sv $^" \
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-p "hierarchy -top ${TOP}" \
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-p "synth_ecp5 -abc9 -json $@" \
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$(BUILDDIR)/%.config: $(PIN_DEF) $(BUILDDIR)/toplevel.json
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nextpnr-ecp5 --${DEVICE} --package CABGA381 --timing-allow-fail --freq 25 --textcfg $@ --json $(filter-out $<,$^) --lpf $<
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$(BUILDDIR)/toplevel.bit: $(BUILDDIR)/toplevel.config
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ecppack --compress $^ $@
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clean:
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rm -rf ${BUILDDIR} obj_dir
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.SECONDARY:
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.PHONY: compile clean prog dfu sim
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