78 lines
1.5 KiB
Systemverilog
78 lines
1.5 KiB
Systemverilog
module top (
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// Main 12M clock
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input logic clk12m,
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// Accelerometer
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output logic acc_sclk,
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output logic acc_mosi,
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input logic acc_miso,
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output logic acc_cs,
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input logic acc_int1,
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input logic acc_int2,
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// Onboard button
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input logic btn,
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// Header GPIO
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inout logic [14:0] gpio_d,
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input logic [7:0] gpio_a,
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// Onboard LEDs
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output logic [8:1] led,
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// PMOD header
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inout logic [8:1] pmod,
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// Onboard RAM
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output logic ram_clk,
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inout logic [15:0] ram_data,
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output logic [13:0] ram_addr,
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output logic [1:0] ram_dqm,
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output logic [1:0] ram_bs,
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output logic ram_cke,
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output logic ram_ras,
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output logic ram_cas,
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output logic ram_we,
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output logic ram_cs
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);
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wire pixel_clk;
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PLL p_clk_pll (clk12m, pixel_clk);
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wire h_sync, v_sync;
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assign gpio_d[13] = h_sync;
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assign gpio_d[12] = v_sync;
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reg [9:0] h_counter;
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reg [9:0] v_counter;
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// VGA 640 x 480 @ 60 Hz
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// pixel_clk 25.175MHz
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always @(posedge pixel_clk) begin
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if (h_counter < 799) begin
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h_counter <= h_counter + 1;
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end else begin
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// reset scanline
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h_counter <= 1'b0;
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// step v_counter after hline
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if (v_counter < 524) begin
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v_counter <= v_counter + 1;
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end else begin
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v_counter <= 1'b0;
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end
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end
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end
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// generate sync pulses
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assign h_sync = (h_counter < 96) ? 1'b1 : 1'b0;
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assign v_sync = (v_counter < 2) ? 1'b1 : 1'b0;
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assign led[1] = h_sync;
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assign led[2] = v_sync;
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assign led[3] = pixel_clk;
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assign led[8:4] = v_counter;
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endmodule
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