benkyd/fpga-basics
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Benjamin Kyd 63fa6db8d6 reg
2022-06-05 00:55:14 +01:00
Max10_VGA
reg
2022-06-05 00:55:14 +01:00
Max1000 Template
initial
2022-05-26 23:54:01 +01:00
.gitignore
initial
2022-05-26 23:54:01 +01:00
Description
A collection of multiple basic FPGA projects on various development boards
78 KiB
Languages
Verilog 70.1%
Tcl 17.9%
SystemVerilog 7.6%
Makefile 2.8%
C++ 1.6%