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Benjamin Kyd
2022-06-05 00:55:14 +01:00
parent 8d65a966cb
commit 63fa6db8d6
6 changed files with 25 additions and 14 deletions
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4
Max10_VGA/Max10_VGA.qsf
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@@ -20,10 +20,10 @@ set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "ViewDraw (Symbol)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VIEWDRAW -section_id eda_board_design_symbol
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "IBIS (Signal Integrity)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT IBIS -section_id eda_board_design_signal_integrity
set_global_assignment -name VCCA_USER_VOLTAGE 3.0V
set_global_assignment -name VCCA_USER_VOLTAGE 3.3V
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF

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Max10_VGA/Max10_VGA.qws
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1
Max10_VGA/top.sv
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@@ -12,6 +12,7 @@ module top (
wire vsync_pulse, hsync_pulse;
// 1111111111 = NO DRAW
wire [10:0] scan_pos_x;
wire [10:0] scan_pos_y;

18
Max10_VGA/top_tb.sv
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@@ -4,20 +4,12 @@ module tb();
reg clk = 1'b0;
wire v_h_sync;
wire v_v_sync;
wire v_v_sync;////////////////////////////////
wire [10:0] scan_pos_x;
wire [10:0] scan_pos_y;
wire [2:0] rgb;
VGA_Signal_Gen VGA_Signal_Gen_Inst(
.pixel_clk(clk),
.scan_x(scan_pos_x),
.scan_y(scan_pos_y),
.h_sync(v_h_sync),
.v_sync(v_v_sync)
);
VGA_Test_Screen VGA_Test_Screen_Inst(
.pixel_clk(clk),
@@ -26,6 +18,14 @@ module tb();
.rgb(rgb)
);
VGA_Signal_Gen VGA_Signal_Gen_Inst(
.pixel_clk(clk),
.scan_x(scan_pos_x),
.scan_y(scan_pos_y),
.h_sync(v_h_sync),
.v_sync(v_v_sync)
);
// 25MHz clock
always #20 clk <= ~clk;

9
Max10_VGA/vga_controller.sv
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@@ -1,4 +1,8 @@
module VGA_Signal_Gen(
module VGA_Signal_Gen
#(parameter TOTAL_COLS = 800,
parameter TOTAL_ROWS = 525,
parameter ACTIVE_COLS = 640,
parameter ACTIVE_ROWS = 480)(
input wire pixel_clk,
output wire [10:0] scan_x,
output wire [10:0] scan_y,
@@ -30,5 +34,8 @@ module VGA_Signal_Gen(
// generate sync pulses
assign h_sync = ~(h_counter <= 96);
assign v_sync = ~(v_counter <= 2);
assign scan_x = h_counter + 48;
assign scan_y = v_counter + 33;
endmodule

7
Max10_VGA/vga_test_screen.sv
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@@ -2,11 +2,14 @@ module VGA_Test_Screen(
input wire pixel_clk,
input wire [10:0] x,
input wire [10:0] y,
output wire [2:0] rgb
output reg [2:0] rgb
);
always @(posedge pixel_clk) begin
rgb[2:2] = 1;
if (x > 20) begin
rgb[1] <= 1;
end
end
endmodule