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10 Commits
4e96b00f95 ... master

Author SHA1 Message Date
Ben Kyd
55fb8e3be4 most of the way there 2025-07-10 22:10:05 +01:00
Ben Kyd
9f12c776ee not good nuf 2025-07-09 22:33:12 +01:00
Ben Kyd
617f331c81 spi 2025-07-07 23:41:44 +01:00
Ben Kyd
8671169b26 epic testbenches 2025-07-07 15:48:53 +01:00
Ben Kyd
cb009937d5 testbenches 2025-07-07 15:19:09 +01:00
Ben Kyd
543afdb68f status 2025-07-07 15:18:38 +01:00
Ben Kyd
57aecc5512 gitignore 2025-07-07 15:18:14 +01:00
Ben Kyd
0cf72c6c3b TEsting yosys 2025-07-07 12:11:19 +01:00
Benjamin Kyd
279813aad7 that again 2022-06-06 21:20:05 +01:00
Benjamin Kyd
65bf958d6f raytracing and remove of redundant files 2022-06-06 21:05:35 +01:00
49 changed files with 8727 additions and 103 deletions
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8
.gitignore vendored
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Blink/
max1000_template/
build/
bin/
.obj_dir/
obj_dir/
*.nvim/
.cache/
*.vcd/

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+incdir+/home/benk/projects/fpga-basics/Max10_RT
+incdir+/home/benk/projects/fpga-basics/Max10_VGA
+incdir+/home/benk/projects/fpga-basics/Max1000 Template
+incdir+/home/benk/projects/fpga-basics/Verilator_Tests/clk
+incdir+/home/benk/projects/fpga-basics/Verilator_Tests/spi
+incdir+/home/benk/projects/fpga-basics/Max10_RT
+incdir+/home/benk/projects/fpga-basics/Max10_VGA
+incdir+/home/benk/projects/fpga-basics/Max1000 Template
+incdir+/home/benk/projects/fpga-basics/Verilator_Tests/clk
+incdir+/home/benk/projects/fpga-basics/Verilator_Tests/spi

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# Quartus generated files
.qsys_edit/
board/
db/
incremental_db/
output_files/
simulation/
timing/
# VIM swap files
*.swp
*.swo
# OS-specific litter files
Thumbs.db
.DS_Store

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QUARTUS_VERSION = "17.1"
DATE = "13:14:16 February 14, 2018"
# Revisions
PROJECT_REVISION = "Max10_RT"

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set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M08SAU169C8G
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:14:16 FEBRUARY 14, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Precision Synthesis"
set_global_assignment -name EDA_LMF_FILE mentor.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "Stamp (Timing)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT STAMP -section_id eda_board_design_timing
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "ViewDraw (Symbol)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VIEWDRAW -section_id eda_board_design_symbol
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "IBIS (Signal Integrity)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT IBIS -section_id eda_board_design_signal_integrity
set_global_assignment -name VCCA_USER_VOLTAGE 3.3V
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# Pin assignments
set_location_assignment PIN_H6 -to clk12m
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk12m
# Clock assignment
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb -section_id tb
set_global_assignment -name EDA_TEST_BENCH_FILE top_tb.sv -section_id tb
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_acc.tcl
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_button.tcl
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_gpio.tcl
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_led.tcl
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_pmod.tcl
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_ram.tcl
set_global_assignment -name SDC_FILE timings.sdc
set_global_assignment -name QIP_FILE PLL.qip
set_global_assignment -name SYSTEMVERILOG_FILE top.sv
set_global_assignment -name SYSTEMVERILOG_FILE top_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE vga_controller.sv
set_global_assignment -name SYSTEMVERILOG_FILE vga_test_screen.sv
set_global_assignment -name SYSTEMVERILOG_FILE raytracer.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Max10_RT/Max10_RT_assignment_defaults.qdf Normal file
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@@ -0,0 +1,806 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 16:03:28 May 24, 2022
#
# -------------------------------------------------------------------------- #
#
# Note:
#
# 1) Do not modify this file. This file was generated
# automatically by the Quartus Prime software and is used
# to preserve global assignments across Quartus Prime versions.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
set_global_assignment -name IP_COMPONENT_INTERNAL Off
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
set_global_assignment -name HC_OUTPUT_DIR hc_output
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
set_global_assignment -name REVISION_TYPE Base -family "Arria V"
set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
set_global_assignment -name DO_COMBINED_ANALYSIS Off
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V"
set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V"
set_global_assignment -name OPTIMIZATION_MODE Balanced
set_global_assignment -name ALLOW_REGISTER_MERGING On
set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V"
set_global_assignment -name MUX_RESTRUCTURE Auto
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
set_global_assignment -name ENABLE_IP_DEBUG Off
set_global_assignment -name SAVE_DISK_SPACE On
set_global_assignment -name OCP_HW_EVAL Enable
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
set_global_assignment -name SAFE_STATE_MACHINE Off
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
set_global_assignment -name PARALLEL_SYNTHESIS On
set_global_assignment -name DSP_BLOCK_BALANCING Auto
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
set_global_assignment -name NOT_GATE_PUSH_BACK On
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
set_global_assignment -name IGNORE_SOFT_BUFFERS On
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
set_global_assignment -name AUTO_LCELL_INSERTION On
set_global_assignment -name CARRY_CHAIN_LENGTH 48
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
set_global_assignment -name AUTO_CARRY_CHAINS On
set_global_assignment -name AUTO_CASCADE_CHAINS On
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
set_global_assignment -name AUTO_ROM_RECOGNITION On
set_global_assignment -name AUTO_RAM_RECOGNITION On
set_global_assignment -name AUTO_DSP_RECOGNITION On
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
set_global_assignment -name STRICT_RAM_RECOGNITION Off
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
set_global_assignment -name FORCE_SYNCH_CLEAR Off
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
set_global_assignment -name AUTO_RESOURCE_SHARING Off
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
set_global_assignment -name SYNTHESIS_EFFORT Auto
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
set_global_assignment -name PRPOF_ID Off
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
set_global_assignment -name AUTO_MERGE_PLLS On
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
set_global_assignment -name TXPMA_SLEW_RATE Low
set_global_assignment -name ADCE_ENABLED Auto
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
set_global_assignment -name PHYSICAL_SYNTHESIS Off
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
set_global_assignment -name DEVICE AUTO
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
set_global_assignment -name STRATIX_UPDATE_MODE Standard
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
set_global_assignment -name CVP_MODE Off
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
set_global_assignment -name USE_CONF_DONE AUTO
set_global_assignment -name USE_PWRMGT_SCL AUTO
set_global_assignment -name USE_PWRMGT_SDA AUTO
set_global_assignment -name USE_PWRMGT_ALERT AUTO
set_global_assignment -name USE_INIT_DONE AUTO
set_global_assignment -name USE_CVP_CONFDONE AUTO
set_global_assignment -name USE_SEU_ERROR AUTO
set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name USER_START_UP_CLOCK Off
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
set_global_assignment -name ENABLE_VREFA_PIN Off
set_global_assignment -name ENABLE_VREFB_PIN Off
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
set_global_assignment -name ENABLE_NCE_PIN Off
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
set_global_assignment -name CRC_ERROR_CHECKING Off
set_global_assignment -name INTERNAL_SCRUBBING Off
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
set_global_assignment -name PR_READY_OPEN_DRAIN On
set_global_assignment -name ENABLE_CVP_CONFDONE Off
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
set_global_assignment -name OPTIMIZE_SSN Off
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
set_global_assignment -name ECO_REGENERATE_REPORT Off
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
set_global_assignment -name SEED 1
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
set_global_assignment -name SLOW_SLEW_RATE Off
set_global_assignment -name PCI_IO Off
set_global_assignment -name TURBO_BIT On
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
set_global_assignment -name NORMAL_LCELL_INSERT On
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
set_global_assignment -name FITTER_EFFORT "Auto Fit"
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
set_global_assignment -name AUTO_GLOBAL_CLOCK On
set_global_assignment -name AUTO_GLOBAL_OE On
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
set_global_assignment -name PR_DONE_OPEN_DRAIN On
set_global_assignment -name NCEO_OPEN_DRAIN On
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
set_global_assignment -name ENABLE_PR_PINS Off
set_global_assignment -name RESERVE_PR_PINS Off
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
set_global_assignment -name CLAMPING_DIODE Off
set_global_assignment -name TRI_STATE_SPI_PINS Off
set_global_assignment -name UNUSED_TSD_PINS_GND Off
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
set_global_assignment -name SEU_FIT_REPORT Off
set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
set_global_assignment -name COMPRESSION_MODE Off
set_global_assignment -name CLOCK_SOURCE Internal
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
set_global_assignment -name SECURITY_BIT Off
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
set_global_assignment -name GENERATE_TTF_FILE Off
set_global_assignment -name GENERATE_RBF_FILE Off
set_global_assignment -name GENERATE_HEX_FILE Off
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
set_global_assignment -name POR_SCHEME "Instant ON"
set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
set_global_assignment -name POF_VERIFY_PROTECT Off
set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
set_global_assignment -name GENERATE_PMSF_FILES On
set_global_assignment -name START_TIME 0ns
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
set_global_assignment -name SETUP_HOLD_DETECTION Off
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
set_global_assignment -name CHECK_OUTPUTS Off
set_global_assignment -name SIMULATION_COVERAGE On
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name GLITCH_DETECTION Off
set_global_assignment -name GLITCH_INTERVAL 1ns
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
set_global_assignment -name DRC_TOP_FANOUT 50
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
set_global_assignment -name ENABLE_DRC_SETTINGS Off
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
set_global_assignment -name MERGE_HEX_FILE Off
set_global_assignment -name GENERATE_SVF_FILE Off
set_global_assignment -name GENERATE_ISC_FILE Off
set_global_assignment -name GENERATE_JAM_FILE Off
set_global_assignment -name GENERATE_JBC_FILE Off
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
set_global_assignment -name HPS_EARLY_IO_RELEASE Off
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_USE_PVA On
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
set_global_assignment -name POWER_USE_INPUT_FILES Off
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
set_global_assignment -name POWER_TJ_VALUE 25
set_global_assignment -name POWER_USE_TA_VALUE 25
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
set_global_assignment -name POWER_HPS_ENABLE Off
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
set_global_assignment -name IGNORE_PARTITIONS Off
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
set_global_assignment -name EQC_BBOX_MERGE On
set_global_assignment -name EQC_LVDS_MERGE On
set_global_assignment -name EQC_RAM_UNMERGING On
set_global_assignment -name EQC_DFF_SS_EMULATION On
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
set_global_assignment -name EQC_STRUCTURE_MATCHING On
set_global_assignment -name EQC_AUTO_BREAK_CONE On
set_global_assignment -name EQC_POWER_UP_COMPARE Off
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
set_global_assignment -name EQC_AUTO_INVERSION On
set_global_assignment -name EQC_AUTO_TERMINATE On
set_global_assignment -name EQC_SUB_CONE_REPORT Off
set_global_assignment -name EQC_RENAMING_RULES On
set_global_assignment -name EQC_PARAMETER_CHECK On
set_global_assignment -name EQC_AUTO_PORTSWAP On
set_global_assignment -name EQC_DETECT_DONT_CARES On
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ?
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?

23
Max10_RT/Max10_RT_nativelink_simulation.rpt Normal file
View File

@@ -0,0 +1,23 @@
Info: Start Nativelink Simulation process
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used
========= EDA Simulation Settings =====================
Sim Mode : RTL
Family : max10
Quartus root : c:/intelfpga_lite/21.1/quartus/bin64/
Quartus sim root : c:/intelfpga_lite/21.1/quartus/eda/sim_lib
Simulation Tool : questa intel fpga
Simulation Language : verilog
Simulation Mode : GUI
Sim Output File :
Sim SDF file :
Sim dir : simulation\modelsim
=======================================================
Info: Starting NativeLink simulation with Questa Intel FPGA software
Sourced NativeLink script c:/intelfpga_lite/21.1/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File Max10_VGA_run_msim_rtl_verilog.do already exists - backing up current file as Max10_VGA_run_msim_rtl_verilog.do.bak11
Info: Spawning Questa Intel FPGA Simulation software
Info: NativeLink simulation flow was successful

9
Max10_RT/PLL.ppf Normal file
View File

@@ -0,0 +1,9 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="MAX 10" variation_name="PLL" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
</global>
</pinplan>

7
Max10_RT/PLL.qip Normal file
View File

@@ -0,0 +1,7 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "21.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "PLL.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL.ppf"]

306
Max10_RT/PLL.v Normal file
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@@ -0,0 +1,306 @@
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: PLL.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
// ************************************************************
//Copyright (C) 2021 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module PLL (
inclk0,
c0);
input inclk0;
output c0;
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
altpll altpll_component (
.inclk (sub_wire1),
.clk (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 12,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 25,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 83333,
altpll_component.intended_device_family = "MAX 10",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=PLL",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

199
Max10_RT/PLL_bb.v Normal file
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// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: PLL.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
// ************************************************************
//Copyright (C) 2021 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
module PLL (
inclk0,
c0);
input inclk0;
output c0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

4
Max10_RT/PLL_inst.v Normal file
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@@ -0,0 +1,4 @@
PLL PLL_inst (
.inclk0 ( inclk0_sig ),
.c0 ( c0_sig )
);

8
Max10_RT/pins/assignment_acc.tcl Normal file
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@@ -0,0 +1,8 @@
set_location_assignment PIN_L4 -to acc_int2
set_location_assignment PIN_L5 -to acc_cs
set_location_assignment PIN_J5 -to acc_int1
set_location_assignment PIN_K5 -to acc_miso
set_location_assignment PIN_J7 -to acc_mosi
set_location_assignment PIN_J6 -to acc_sclk
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to acc_*

3
Max10_RT/pins/assignment_button.tcl Normal file
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@@ -0,0 +1,3 @@
set_location_assignment PIN_E6 -to btn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to btn

26
Max10_RT/pins/assignment_gpio.tcl Normal file
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@@ -0,0 +1,26 @@
set_location_assignment PIN_H8 -to gpio_d[0]
set_location_assignment PIN_K10 -to gpio_d[1]
set_location_assignment PIN_H5 -to gpio_d[2]
set_location_assignment PIN_H4 -to gpio_d[3]
set_location_assignment PIN_J1 -to gpio_d[4]
set_location_assignment PIN_J2 -to gpio_d[5]
set_location_assignment PIN_L12 -to gpio_d[6]
set_location_assignment PIN_J12 -to gpio_d[7]
set_location_assignment PIN_J13 -to gpio_d[8]
set_location_assignment PIN_K11 -to gpio_d[9]
set_location_assignment PIN_K12 -to gpio_d[10]
set_location_assignment PIN_J10 -to gpio_d[11]
set_location_assignment PIN_H10 -to gpio_d[12]
set_location_assignment PIN_H13 -to gpio_d[13]
set_location_assignment PIN_G12 -to gpio_d[14]
set_location_assignment PIN_E1 -to gpio_a[0]
set_location_assignment PIN_C2 -to gpio_a[1]
set_location_assignment PIN_C1 -to gpio_a[2]
set_location_assignment PIN_D1 -to gpio_a[3]
set_location_assignment PIN_E3 -to gpio_a[4]
set_location_assignment PIN_F1 -to gpio_a[5]
set_location_assignment PIN_E4 -to gpio_a[6]
set_location_assignment PIN_B1 -to gpio_a[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to gpio_*

10
Max10_RT/pins/assignment_led.tcl Normal file
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@@ -0,0 +1,10 @@
set_location_assignment PIN_A8 -to led[1]
set_location_assignment PIN_A9 -to led[2]
set_location_assignment PIN_A11 -to led[3]
set_location_assignment PIN_A10 -to led[4]
set_location_assignment PIN_B10 -to led[5]
set_location_assignment PIN_C9 -to led[6]
set_location_assignment PIN_C10 -to led[7]
set_location_assignment PIN_D8 -to led[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to led*

10
Max10_RT/pins/assignment_pmod.tcl Normal file
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@@ -0,0 +1,10 @@
set_location_assignment PIN_M3 -to pmod[1]
set_location_assignment PIN_L3 -to pmod[2]
set_location_assignment PIN_M2 -to pmod[3]
set_location_assignment PIN_M1 -to pmod[4]
set_location_assignment PIN_N3 -to pmod[5]
set_location_assignment PIN_N2 -to pmod[6]
set_location_assignment PIN_K2 -to pmod[7]
set_location_assignment PIN_K1 -to pmod[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmod*

46
Max10_RT/pins/assignment_ram.tcl Normal file
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@@ -0,0 +1,46 @@
set_location_assignment PIN_D11 -to ram_data[0]
set_location_assignment PIN_G10 -to ram_data[1]
set_location_assignment PIN_F10 -to ram_data[2]
set_location_assignment PIN_F9 -to ram_data[3]
set_location_assignment PIN_E10 -to ram_data[4]
set_location_assignment PIN_D9 -to ram_data[5]
set_location_assignment PIN_G9 -to ram_data[6]
set_location_assignment PIN_F8 -to ram_data[7]
set_location_assignment PIN_F13 -to ram_data[8]
set_location_assignment PIN_E12 -to ram_data[9]
set_location_assignment PIN_E13 -to ram_data[10]
set_location_assignment PIN_D12 -to ram_data[11]
set_location_assignment PIN_C12 -to ram_data[12]
set_location_assignment PIN_B12 -to ram_data[13]
set_location_assignment PIN_B13 -to ram_data[14]
set_location_assignment PIN_A12 -to ram_data[15]
set_location_assignment PIN_E9 -to ram_dqm[0]
set_location_assignment PIN_F12 -to ram_dqm[1]
set_location_assignment PIN_K6 -to ram_addr[0]
set_location_assignment PIN_M5 -to ram_addr[1]
set_location_assignment PIN_N5 -to ram_addr[2]
set_location_assignment PIN_J8 -to ram_addr[3]
set_location_assignment PIN_N10 -to ram_addr[4]
set_location_assignment PIN_M11 -to ram_addr[5]
set_location_assignment PIN_N9 -to ram_addr[6]
set_location_assignment PIN_L10 -to ram_addr[7]
set_location_assignment PIN_M13 -to ram_addr[8]
set_location_assignment PIN_N8 -to ram_addr[9]
set_location_assignment PIN_N4 -to ram_addr[10]
set_location_assignment PIN_M10 -to ram_addr[11]
set_location_assignment PIN_L11 -to ram_addr[12]
set_location_assignment PIN_M12 -to ram_addr[13]
set_location_assignment PIN_N6 -to ram_bs[0]
set_location_assignment PIN_K8 -to ram_bs[1]
set_location_assignment PIN_M4 -to ram_cs
set_location_assignment PIN_M7 -to ram_ras
set_location_assignment PIN_N7 -to ram_cas
set_location_assignment PIN_M9 -to ram_clk
set_location_assignment PIN_M8 -to ram_cke
set_location_assignment PIN_K7 -to ram_we
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ram_*

8
Max10_RT/raytracer.sv Normal file
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@@ -0,0 +1,8 @@
module Raytracer(
input wire pixel_clk,
input reg [10:0] x,
input reg [10:0] y,
output reg [2:0] rgb
);
endmodule

3
Max10_RT/raytracer.sv.bak Normal file
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@@ -0,0 +1,3 @@
module Raytracer();
endmodule

8
Max10_RT/timings.sdc Normal file
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@@ -0,0 +1,8 @@
# Clock constraints
create_clock -name "clk12m" -period 83.333ns [get_ports {clk12m}]
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty

45
Max10_RT/top.sv Normal file
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@@ -0,0 +1,45 @@
module top (
// Main 12M clock
input logic clk12m,
// Header GPIO
inout logic [14:0] gpio_d,
// Onboard LEDs
output logic [8:1] led
);
wire pixel_clk;
PLL p_clk_pll (clk12m, pixel_clk);
wire [2:0] rgb;
wire [9:0] hcounter;
wire [9:0] vcounter;
wire hsync;
wire vsync;
VGA_Signal_Gen VGA_Signal_Gen_Inst(
.pixel_clk(pixel_clk),
.hcounter(hcounter),
.vcounter(vcounter),
.hsync(hsync),
.vsync(vsync)
);
VGA_Test_Screen VGA_Test_Screen_Inst(
.pixel_clk(pixel_clk),
.x(hcounter),
.y(vcounter),
.rgb(rgb)
);
assign gpio_d[14] = hsync;
assign gpio_d[13] = vsync;
assign gpio_d[11:9] = rgb;
// OopSS, need a fake ground pin here
assign gpio_d[6] = 0;
assign led[1] = vsync;
endmodule

38
Max10_RT/top_tb.sv Normal file
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@@ -0,0 +1,38 @@
`timescale 1 ns / 100 ps
module tb();
reg clk = 1'b0;
wire v_h_sync;
wire v_v_sync;////////////////////////////////
wire [10:0] scan_pos_x;
wire [10:0] scan_pos_y;
wire [2:0] rgb;
VGA_Test_Screen VGA_Test_Screen_Inst(
.pixel_clk(clk),
.x(scan_pos_x),
.y(scan_pos_y),
.rgb(rgb)
);
VGA_Signal_Gen VGA_Signal_Gen_Inst(
.pixel_clk(clk),
.scan_x(scan_pos_x),
.scan_y(scan_pos_y),
.h_sync(v_h_sync),
.v_sync(v_v_sync)
);
// 25MHz clock
always #20 clk <= ~clk;
initial begin
$display($time, " Starting the Simulation");
#1000
$finish();
end
endmodule

34
Max10_RT/vga_controller.sv Normal file
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@@ -0,0 +1,34 @@
module VGA_Signal_Gen(
input wire pixel_clk,
output reg [9:0] hcounter,
output reg [9:0] vcounter,
output wire hsync,
output wire vsync
);
always @(posedge pixel_clk) begin
if(hcounter == 799) begin
hcounter <= 0;
if(vcounter == 524)
vcounter <= 0;
else
vcounter <= vcounter + 1'b1;
end
else
hcounter <= hcounter + 1'b1;
if (vcounter >= 490 && vcounter < 492)
vsync <= 1'b0;
else
vsync <= 1'b1;
if (hcounter >= 656 && hcounter < 752)
hsync <= 1'b0;
else
hsync <= 1'b1;
end
endmodule

31
Max10_RT/vga_test_screen.sv Normal file
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@@ -0,0 +1,31 @@
module VGA_Test_Screen(
input wire pixel_clk,
input reg [10:0] x,
input reg [10:0] y,
output reg [2:0] rgb
);
always @ (posedge pixel_clk) begin
if (x < 80 && y < 480)
rgb <= 3'b111;
else if (x < 160 && y < 480)
rgb <= 3'b110;
else if (x < 240 && y < 480)
rgb <= 3'b101;
else if (x < 320 && y < 480)
rgb <= 3'b100;
else if (x < 400 && y < 480)
rgb <= 3'b011;
else if (x < 480 && y < 480)
rgb <= 3'b010;
else if (x < 560 && y < 480)
rgb <= 3'b001;
else if (x < 640 && y < 480)
rgb <= 3'b000;
else
rgb <= 3'b000;
end
endmodule

BIN
Max10_VGA/Max10_VGA.qws Normal file
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Binary file not shown.

22
Max10_VGA/README.md
View File

@@ -1,22 +0,0 @@
# MAX1000 Template
Howdy!
Here you may find a template Quartus II project for the Arrow/Trenz FPGA dev
board MAX1000. This is a rather nice board, but somehow lacking documentation.
## What do I get?
This contains a fully featured Quartus II project, complete with pin assignments
and naming, along with clock config and sample top module.
## TODO
- Makefile to build from the CLI and avoid the Quartus GUI altogether
- Integrate some docs with pinouts, etc
- Figure out how to #@&! reset registers
## Licence
DWTFYW

42
Max10_VGA/top.sv.bak
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@@ -1,42 +0,0 @@
module max1000_template (
// Main 12M clock
input logic clk12m,
// Accelerometer
output logic acc_sclk,
output logic acc_mosi,
input logic acc_miso,
output logic acc_cs,
input logic acc_int1,
input logic acc_int2,
// Onboard button
input logic btn,
// Header GPIO
inout logic [14:0] gpio_d,
input logic [7:0] gpio_a,
// Onboard LEDs
output logic [8:1] led,
// PMOD header
inout logic [8:1] pmod,
// Onboard RAM
output logic ram_clk,
inout logic [15:0] ram_data,
output logic [13:0] ram_addr,
output logic [1:0] ram_dqm,
output logic [1:0] ram_bs,
output logic ram_cke,
output logic ram_ras,
output logic ram_cas,
output logic ram_we,
output logic ram_cs
);
// This is the top module, enter your design here
// Happy HDL :]
endmodule

24
Max10_VGA/top_tb.sv.bak
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@@ -1,24 +0,0 @@
`timescale 1 ns / 100 ps
module tb();
reg clk = 1'b0;
reg [14:0] v_gpio_d;
reg [8:1] v_led;
VGA_Controller VGA_Controller_Inst(
.pixel_clk(clk),
.gpio_d(v_gpio_d)
);
// 25MHz clock
always #5 clk <= ~clk;
initial begin
$display($time, " Starting the Simulation");
#1000
$finish();
end
endmodule

8
Max10_VGA/vga_controller.sv.bak
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@@ -1,8 +0,0 @@
module VGA_Controller(
input wire pixel_clk,
inout logic [14:0] gpio_d,
output logic [8:1] led
};
endmodule

5
Max10_VGA/vga_test_screen.sv.bak
View File

@@ -1,5 +0,0 @@
VGA_Test_Screen(
input wire [10:0] scan_pos_x,
input wire [10:0] scan_pos_y,
output wire [2:0] rgb,
);

3
readme.md → README.md
View File

@@ -4,4 +4,5 @@ A Collection of simple FPGA Projects to learn the basics of FPGA programming.
| Dev Board | FPGA | Project | Description |
| -- | -- | -- | -- |
| [Max 1000](https://vhdplus.com/docs/components/max1000/) | MAX10M08 | [VGA Driver](/Max10_VGA/) | VGA Driver |
| [Max 1000](https://vhdplus.com/docs/components/max1000/) | MAX10M08 | [VGA Driver](/Max10_VGA/) | VGA Driver |
| | | [Raytracing](/Max10_Raytracer/) | VGA Output Raytracing |

4
Verilator_Tests/clk/Makefile Normal file
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@@ -0,0 +1,4 @@
VERILOG = top.v
DEVICE = um-45k
include ./ulx4m.mk

29
Verilator_Tests/clk/sim_main.cpp Normal file
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@@ -0,0 +1,29 @@
#include "Vtop.h"
#include "verilated.h"
#include "verilated_vcd_c.h"
int main(int argc, char** argv) {
Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true);
Vtop* top = new Vtop;
VerilatedVcdC* tfp = new VerilatedVcdC;
top->trace(tfp, 99);
tfp->open("wave.vcd");
int clk = 0;
for (int time = 0; time < 50000; time++) {
// Toggle clk every 20 time units (simulate 25 MHz)
if ((time % 20) == 0)
clk = !clk;
top->clk_25mhz = clk;
top->eval();
tfp->dump(time);
}
tfp->close();
delete top;
return 0;
}

5
Verilator_Tests/clk/top.v Normal file
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@@ -0,0 +1,5 @@
module top (
input clk_25mhz
);
endmodule

22
Verilator_Tests/clk/top_tb.v Normal file
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@@ -0,0 +1,22 @@
// Copyright 2025 Benjamin Kyd, All Rights Reserved
`timescale 1ns / 1ps
module top_tb;
reg clk_25mhz = 0;
top uut (
.clk_25mhz(clk_25mhz),
);
always #20 clk_25mhz = ~clk_25mhz;
initial begin
$dumpfile("top_tb.vcd");
$dumpvars(0, top_tb);
#500 $finish;
end
endmodule

47
Verilator_Tests/clk/ulx4m.mk Normal file
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@@ -0,0 +1,47 @@
PIN_DEF ?= ./ulx4m_v002.lpf
DEVICE ?= 85k
BUILDDIR = bin
TOP ?= top
VERILOG ?= $(wildcard *.v)
compile: $(BUILDDIR)/toplevel.bit
prog: $(BUILDDIR)/toplevel.bit
fujprog $^
dfu: $(BUILDDIR)/toplevel.bit
dfu-util -a 0 -D $^ -R
sim: $(BUILDDIR)/sim.out
$^
$(BUILDDIR)/sim.out: $(VERILOG) sim_main.cpp
mkdir -p $(BUILDDIR)
verilator -Wall --cc $(VERILOG) \
--top-module top \
--exe sim_main.cpp \
--build -CFLAGS "-O2 -std=c++17" \
--trace \
--Wno-UNUSEDSIGNAL \
--Wno-UNDRIVEN \
--timing
cp obj_dir/Vtop $@
$(BUILDDIR)/toplevel.json: $(VERILOG)
mkdir -p $(BUILDDIR)
yosys \
-p "read -sv $^" \
-p "hierarchy -top ${TOP}" \
-p "synth_ecp5 -abc9 -json $@" \
$(BUILDDIR)/%.config: $(PIN_DEF) $(BUILDDIR)/toplevel.json
nextpnr-ecp5 --${DEVICE} --package CABGA381 --timing-allow-fail --freq 25 --textcfg $@ --json $(filter-out $<,$^) --lpf $<
$(BUILDDIR)/toplevel.bit: $(BUILDDIR)/toplevel.config
ecppack --compress $^ $@
clean:
rm -rf ${BUILDDIR} obj_dir
.SECONDARY:
.PHONY: compile clean prog dfu sim

397
Verilator_Tests/clk/ulx4m_v002.lpf Normal file
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@@ -0,0 +1,397 @@
BLOCK RESETPATHS;
BLOCK ASYNCPATHS;
## ULX4M-LS v0.0.2
# The clock "usb" and "gpdi" sheet
LOCATE COMP "clk_25mhz" SITE "G2";
IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33;
FREQUENCY PORT "clk_25mhz" 25 MHZ;
# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash
# write to FLASH possible any time from JTAG:
# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;
# write to FLASH possible from user bitstream:
SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
## LED indicators "blinkey" and "gpio" sheet
LOCATE COMP "led[3]" SITE "C1";
LOCATE COMP "led[2]" SITE "B3";
LOCATE COMP "led[1]" SITE "B1";
LOCATE COMP "led[0]" SITE "B2";
IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
## Buttons "blinkey" and "gpio" sheet
LOCATE COMP "btn[1]" SITE "C3";
LOCATE COMP "btn[2]" SITE "C2";
IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
## SPI Flash chip "flash" sheet
LOCATE COMP "flash_csn" SITE "R2";
LOCATE COMP "flash_clk" SITE "U3";
LOCATE COMP "flash_mosi" SITE "W2";
LOCATE COMP "flash_miso" SITE "V2";
LOCATE COMP "flash_holdn" SITE "W1";
LOCATE COMP "flash_wpn" SITE "Y2";
#LOCATE COMP "flash_csspin" SITE "AJ3";
#LOCATE COMP "flash_initn" SITE "AG4";
#LOCATE COMP "flash_done" SITE "AJ4";
#LOCATE COMP "flash_programn" SITE "AH4";
#LOCATE COMP "flash_cfg_select[0]" SITE "AM4";
#LOCATE COMP "flash_cfg_select[1]" SITE "AL4";
#LOCATE COMP "flash_cfg_select[2]" SITE "AK4";
IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
## SD card "sdcard", "usb" sheet
LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14 CM4_GPIO12
LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi_GPIO15 CM4_GPIO27
LOCATE COMP "sd_d[0]" SITE "J3"; # sd_dat0_do (MISO) WiFi_GPIO2 CM4_GPIO4
LOCATE COMP "sd_d[1]" SITE "H1"; # sd_dat1_irq WiFi_GPIO4 CM4_GPIO3
LOCATE COMP "sd_d[2]" SITE "K1"; # sd_dat2 WiFi_GPIO12 CM4_GPIO2
LOCATE COMP "sd_d[3]" SITE "K2"; # sd_dat3_csn WiFi_GPIO13 CM4_GPIO14
LOCATE COMP "sd_wp" SITE "P5"; # not connected
LOCATE COMP "sd_cdn" SITE "N5"; # not connected
IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement
IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "sd_pwr_on" SITE "U17"; # J2_5- GN14
IOBUF PORT "sd_pwr_on" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
## Second USB port "US2" going directly into FPGA "usb", "ram" sheet
LOCATE COMP "usb_fpga_dp" SITE "E16"; # same on ULX3S and ULX4M
LOCATE COMP "usb_fpga_dn" SITE "F16"; # same on ULX3S and ULX4M
IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16;
IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16;
LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # single-ended bidirectional same on ULX3S and ULX4M
LOCATE COMP "usb_fpga_bd_dn" SITE "E15"; # single-ended bidirectional same on ULX3S and ULX4M
IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "usb_fpga_pu_dp" SITE "A2"; # pull up/down control
LOCATE COMP "usb_fpga_pu_dn" SITE "A3";
IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
IOBUF PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
LOCATE COMP "usb_fpga_otg_id" SITE "A4";
IOBUF PORT "usb_fpga_otg_id" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "n_extrst" SITE "U16";
IOBUF PORT "n_extrst" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
## JTAG ESP-32 "usb" sheet
# connected to FT231X and ESP-32
# commented out because those are dedicated pins, not directly useable as GPIO
# but could be used by some vendor-specific JTAG bridging (boundary scan) module
#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives
#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits
#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives
#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives
#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
## SDRAM "ram" sheet
LOCATE COMP "sdram_clk" SITE "G19";
LOCATE COMP "sdram_cke" SITE "G20";
LOCATE COMP "sdram_csn" SITE "P18";
LOCATE COMP "sdram_wen" SITE "N20";
LOCATE COMP "sdram_rasn" SITE "M18";
LOCATE COMP "sdram_casn" SITE "N18";
LOCATE COMP "sdram_a[0]" SITE "L19";
LOCATE COMP "sdram_a[1]" SITE "L20";
LOCATE COMP "sdram_a[2]" SITE "M19";
LOCATE COMP "sdram_a[3]" SITE "H17";
LOCATE COMP "sdram_a[4]" SITE "F20";
LOCATE COMP "sdram_a[5]" SITE "F18";
LOCATE COMP "sdram_a[6]" SITE "E19";
LOCATE COMP "sdram_a[7]" SITE "F19";
LOCATE COMP "sdram_a[8]" SITE "E20";
LOCATE COMP "sdram_a[9]" SITE "C20";
LOCATE COMP "sdram_a[10]" SITE "N19";
LOCATE COMP "sdram_a[11]" SITE "D20";
LOCATE COMP "sdram_a[12]" SITE "E18";
LOCATE COMP "sdram_ba[0]" SITE "L18";
LOCATE COMP "sdram_ba[1]" SITE "M20";
LOCATE COMP "sdram_dqm[0]" SITE "P20";
LOCATE COMP "sdram_dqm[1]" SITE "D19";
LOCATE COMP "sdram_d[0]" SITE "U20";
LOCATE COMP "sdram_d[1]" SITE "T20";
LOCATE COMP "sdram_d[2]" SITE "U19";
LOCATE COMP "sdram_d[3]" SITE "T19";
LOCATE COMP "sdram_d[4]" SITE "T18";
LOCATE COMP "sdram_d[5]" SITE "T17";
LOCATE COMP "sdram_d[6]" SITE "R20";
LOCATE COMP "sdram_d[7]" SITE "P19";
LOCATE COMP "sdram_d[8]" SITE "H20";
LOCATE COMP "sdram_d[9]" SITE "J19";
LOCATE COMP "sdram_d[10]" SITE "K18";
LOCATE COMP "sdram_d[11]" SITE "J18";
LOCATE COMP "sdram_d[12]" SITE "H18";
LOCATE COMP "sdram_d[13]" SITE "J16";
LOCATE COMP "sdram_d[14]" SITE "K19";
LOCATE COMP "sdram_d[15]" SITE "J17";
IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
# GPDI differential interface (Video) "gpdi" sheet
LOCATE COMP "gpdi_dp[0]" SITE "F17"; # Blue +
LOCATE COMP "gpdi_dn[0]" SITE "G18"; # Blue -
LOCATE COMP "gpdi_dp[1]" SITE "D18"; # Green +
LOCATE COMP "gpdi_dn[1]" SITE "E17"; # Green -
LOCATE COMP "gpdi_dp[2]" SITE "C18"; # Red +
LOCATE COMP "gpdi_dn[2]" SITE "D17"; # Red -
LOCATE COMP "gpdi_dp[3]" SITE "J20"; # Clock +
LOCATE COMP "gpdi_dn[3]" SITE "K20"; # Clock -
#LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet +
#LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet -
LOCATE COMP "gpdi_cec" SITE "A18";
#LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC
#LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12
IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "gpdi_dp[4]" SITE "B9"; # Blue +
#LOCATE COMP "gpdi_dn[4]" SITE "C10"; # Blue -
LOCATE COMP "gpdi_dp[5]" SITE "A7"; # Green +
#LOCATE COMP "gpdi_dn[5]" SITE "A8"; # Green -
LOCATE COMP "gpdi_dp[6]" SITE "C8"; # Red +
#LOCATE COMP "gpdi_dn[6]" SITE "B8"; # Red -
LOCATE COMP "gpdi_dp[7]" SITE "B11"; # Clock +
#LOCATE COMP "gpdi_dn[7]" SITE "C11"; # Clock -
IOBUF PORT "gpdi_dp[4]" IO_TYPE=LVCMOS33D DRIVE=4;
IOBUF PORT "gpdi_dn[4]" IO_TYPE=LVCMOS33D DRIVE=4;
IOBUF PORT "gpdi_dp[5]" IO_TYPE=LVCMOS33D DRIVE=4;
IOBUF PORT "gpdi_dn[5]" IO_TYPE=LVCMOS33D DRIVE=4;
IOBUF PORT "gpdi_dp[6]" IO_TYPE=LVCMOS33D DRIVE=4;
IOBUF PORT "gpdi_dn[6]" IO_TYPE=LVCMOS33D DRIVE=4;
IOBUF PORT "gpdi_dp[7]" IO_TYPE=LVCMOS33D DRIVE=4;
IOBUF PORT "gpdi_dn[7]" IO_TYPE=LVCMOS33D DRIVE=4;
# wifi - do not use together with CM4 GPIO
LOCATE COMP "wifi_gpio0" SITE "U1";
LOCATE COMP "wifi_gpio2" SITE "K4"; # sd_d0_do (MISO) WiFi GPIO2
LOCATE COMP "wifi_gpio4" SITE "J5"; # sd_d1_irq WiFi GPIO4
LOCATE COMP "wifi_gpio5" SITE "U5"; #
LOCATE COMP "wifi_gpio12" SITE "K5"; # sd_d2 WiFi_GPIO12
LOCATE COMP "wifi_gpio13" SITE "L4"; # sd_d3_csn WiFi_GPIO13
LOCATE COMP "wifi_gpio14" SITE "L5"; # sd_clk WiFi_GPIO14
LOCATE COMP "wifi_gpio15" SITE "N16"; # sd_cmd_di (MOSI) WiFi GPIO15
LOCATE COMP "wifi_gpio19" SITE "P4";
LOCATE COMP "wifi_gpio21" SITE "P17";
LOCATE COMP "wifi_gpio22" SITE "P16";
LOCATE COMP "wifi_gpio25" SITE "L16";
LOCATE COMP "wifi_gpio26" SITE "N17";
LOCATE COMP "wifi_gpio27" SITE "G16";
LOCATE COMP "wifi_gpio33" SITE "H16";
LOCATE COMP "wifi_gpio34" SITE "V4";
LOCATE COMP "wifi_gpio35" SITE "N17";
IOBUF PORT "wifi_gpio0" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio2" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # pull down or drive 0 for esp32 programming
IOBUF PORT "wifi_gpio4" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio5" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio12" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio13" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # pull down or drive 0 for esp32 programming
IOBUF PORT "wifi_gpio14" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio15" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio19" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio21" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio22" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio25" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio26" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio27" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio33" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio34" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio35" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "ftdi_txden" SITE "T1"; # FTDI_TXDEN
LOCATE COMP "LED1_HAT" SITE "N5"; # LED1 on HAT
LOCATE COMP "wifi_en" SITE "U18";# WIFI_EN
LOCATE COMP "ftdi_txd" SITE "N4"; # FTDI_TXD
LOCATE COMP "ftdi_rxd" SITE "N3"; # FTDI_RXD
LOCATE COMP "wifi_txd" SITE "P5"; # WIFI_TXD
LOCATE COMP "wifi_rxd" SITE "V1"; # WIFI_RXD
IOBUF PORT "ftdi_txden" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "LED1_HAT" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "ftdi_txd" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "ftdi_rxd" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "btn[3]" SITE "E3";
LOCATE COMP "btn[4]" SITE "E4";
LOCATE COMP "btn[5]" SITE "E5";
LOCATE COMP "btn[6]" SITE "H5";
LOCATE COMP "btn[0]" SITE "H4";
LOCATE COMP "nc1" SITE "F2";
LOCATE COMP "sw" SITE "G3";
IOBUF PORT "btn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "btn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "btn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "btn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "btn[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "nc1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sw[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
## CM4 GPIO
LOCATE COMP "gpio[0]" SITE "R16"; # SDA0 - WIFI_GPIO21
LOCATE COMP "gpio[1]" SITE "R17"; # SCL0 - WIFI_GPIO22
LOCATE COMP "gpio[2]" SITE "K5"; # SD_D2 - ESP32 SD share
LOCATE COMP "gpio[3]" SITE "J5"; # SD_D1 - ESP32 SD share
LOCATE COMP "gpio[4]" SITE "K4"; # SD_D0 - ESP32 SD share
LOCATE COMP "gpio[5]" SITE "H16"; # WIFI_GPIO33
LOCATE COMP "gpio[6]" SITE "R1"; # BTN1 on HAT
LOCATE COMP "gpio[7]" SITE "P3"; # BTN2 on HAT
LOCATE COMP "gpio[8]" SITE "P4"; # WIFI_GPIO19
LOCATE COMP "gpio[9]" SITE "G16"; # WIFI_GPIO27
LOCATE COMP "gpio[10]" SITE "N17";# WIFI_GPIO26
LOCATE COMP "gpio[11]" SITE "L16";# WIFI_GPIO25
LOCATE COMP "gpio[12]" SITE "C4"; # FPGA TDI do not use - not connected!
LOCATE COMP "gpio[13]" SITE "T1"; # FTDI_TXDEN
LOCATE COMP "gpio[14]" SITE "L4"; # SD_D3 - ESP32 SD share
LOCATE COMP "gpio[15]" SITE "L5"; # SD_CLK - ESP32 SD share
LOCATE COMP "gpio[16]" SITE "B4"; # FPGA TDO do not use - not connected!
LOCATE COMP "gpio[17]" SITE "M17";# WIFI_GPIO35
LOCATE COMP "gpio[18]" SITE "N5"; # LED1 on HAT
LOCATE COMP "gpio[19]" SITE "U1"; # WIFI_GPIO0
LOCATE COMP "gpio[20]" SITE "E4"; # FPGA TCK do not use - not connected!
LOCATE COMP "gpio[21]" SITE "D5"; # FPGA TMS do not use - not connected!
LOCATE COMP "gpio[22]" SITE "U18";# WIFI_EN
LOCATE COMP "gpio[23]" SITE "N4"; # FTDI_TXD
LOCATE COMP "gpio[24]" SITE "N3"; # FTDI_RXD
LOCATE COMP "gpio[25]" SITE "P5"; # WIFI_TXD
LOCATE COMP "gpio[26]" SITE "V1"; # WIFI_RXD
LOCATE COMP "gpio[27]" SITE "N16";# SD_CMD - ESP32 SD share
IOBUF PORT "gpio[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[16]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[17]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[18]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[19]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[20]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[21]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[22]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[23]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[24]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[25]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[26]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[27]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
## DSI
#
LOCATE COMP "dsiRX0_dp[0]" SITE "B12"; # Clk +
LOCATE COMP "dsiRX0_dn[0]" SITE "C12"; # Clk -
LOCATE COMP "dsiRX0_dp[1]" SITE "A12"; # DSI RX D0 +
LOCATE COMP "dsiRX0_dn[1]" SITE "A13"; # DSI RX D0 -
LOCATE COMP "dsiRX0_dp[2]" SITE "B13"; # DSI RX D1 +
LOCATE COMP "dsiRX0_dn[2]" SITE "C13"; # DSI RX D1 -
LOCATE COMP "dsiTX0_dp[0]" SITE "D12"; # Clk +
LOCATE COMP "dsiTX0_dn[0]" SITE "E12"; # Clk -
LOCATE COMP "dsiTX0_dp[1]" SITE "D13"; # DSI TX D0 +
LOCATE COMP "dsiTX0_dn[1]" SITE "E13"; # DSI TX D0 -
LOCATE COMP "dsiTX0_dp[2]" SITE "A14"; # DSI TX D1 +
LOCATE COMP "dsiTX0_dn[2]" SITE "C14"; # DSI TX D1 -
IOBUF PORT "dsiRX0_dp[0]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiRX0_dn[0]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiRX0_dp[1]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiRX0_dn[1]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiRX0_dp[2]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiRX0_dn[2]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiTX0_dp[0]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiTX0_dp[0]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiTX0_dp[1]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiTX0_dp[1]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiTX0_dp[2]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiTX0_dp[2]" IO_TYPE=LVCMOS12 ;
## PROGRAMN (reload bitstream from FLASH, exit from bootloader)
# PCB v2.0.5 and higher
LOCATE COMP "user_programn" SITE "M4";
IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5)
# on PCB v1.7 shutdown is not connected to FPGA
LOCATE COMP "shutdown" SITE "G16"; # FPGA receives
IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;

5012
Verilator_Tests/clk/wave.vcd Normal file
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File diff suppressed because it is too large Load Diff

4
Verilator_Tests/spi/Makefile Normal file
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@@ -0,0 +1,4 @@
VERILOG = top.v
DEVICE = um-45k
include ./ulx4m.mk

29
Verilator_Tests/spi/sim_main.cpp Normal file
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@@ -0,0 +1,29 @@
#include "Vtop.h"
#include "verilated.h"
#include "verilated_vcd_c.h"
int main(int argc, char** argv) {
Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true);
Vtop* top = new Vtop;
VerilatedVcdC* tfp = new VerilatedVcdC;
top->trace(tfp, 99);
tfp->open("wave.vcd");
int clk = 0;
for (int time = 0; time < 5000; time++) {
// Toggle clk every 20 time units (simulate 25 MHz)
if ((time % 20) == 0)
clk = !clk;
top->clk_25mhz = clk;
top->eval();
tfp->dump(time);
}
tfp->close();
delete top;
return 0;
}

81
Verilator_Tests/spi/spi_master.v Normal file
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module spi_master (
input wire clk,
output reg spi_clk = 0,
input wire start, // Pulse high to begin transfer
input reg [7:0] data_out = 8'd0,
output reg spi_mosi = 0,
output wire [7:0] data_in,
input wire spi_miso,
output reg busy = 0,
output reg spi_cs = 1 // Active low
);
// SPI Mode 0: CPOL = 0, CPHA = 0 (drive on falling, sample on rising)
reg [3:0] bit_cnt = 0;
reg [7:0] shift_reg_in = 0;
reg [7:0] shift_reg_out = 0;
typedef enum logic [1:0] {
IDLE,
CHIP_SEL,
BUSY,
DONE
} state_t;
state_t state = IDLE;
always @(posedge clk) begin
case (state)
IDLE: begin
spi_cs <= 1;
spi_clk <= 0;
busy <= 0;
if (start) begin
state <= CHIP_SEL;
shift_reg_out <= data_out;
bit_cnt <= 0;
end
end
// data is one cycle after CS is brought low
CHIP_SEL: begin
spi_cs <= 0;
busy <= 1;
state <= BUSY;
end
BUSY: begin
if (clk) begin
spi_clk <= ~spi_clk;
// Falling, drive data
if (!spi_clk) begin
spi_mosi <= shift_reg_out[7];
shift_reg_out <= {shift_reg_out[6:0], 1'b0};
end else begin
// Rising, sample data
shift_reg_in <= {shift_reg_in[6:0], spi_miso};
bit_cnt <= bit_cnt + 1;
if (bit_cnt == 7) begin
state <= DONE;
end
end
end
end
DONE: begin
spi_cs <= 1;
data_in <= {shift_reg_in[6:0], spi_miso};
state <= IDLE;
end
endcase
end
endmodule

36
Verilator_Tests/spi/top.v Normal file
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@@ -0,0 +1,36 @@
module top (
input wire clk_25mhz,
output wire spi_clk,
output wire spi_mosi,
input wire spi_miso,
output wire spi_cs
);
// we would prefer fifo
wire[7:0] miso;
wire[7:0] mosi = 8'b01101011;
reg busy = 0;
reg start = 0;
always @(posedge clk_25mhz) begin
start <= 0;
if (!busy && !start) begin
start <= 1;
end
end
spi_master spimaster0(
.clk(clk_25mhz),
.spi_clk(spi_clk),
.start(start),
.data_out(mosi),
.spi_mosi(spi_mosi),
.data_in(miso),
.spi_miso(spi_miso),
.busy(busy),
.spi_cs(spi_cs)
);
endmodule

27
Verilator_Tests/spi/top_tb.v Normal file
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// Copyright 2025 Benjamin Kyd, All Rights Reserved
`timescale 1ns / 1ps
module top_tb;
reg clk_25mhz = 0;
reg spi_clk, spi_mosi, spi_miso, spi_cs;
top uut (
.clk_25mhz(clk_25mhz),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_cs(spi_cs)
);
always #20 clk_25mhz = ~clk_25mhz;
initial begin
$dumpfile("top_tb.vcd");
$dumpvars(0, top_tb);
#500 $finish;
end
endmodule

47
Verilator_Tests/spi/ulx4m.mk Normal file
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@@ -0,0 +1,47 @@
PIN_DEF ?= ./ulx4m_v002.lpf
DEVICE ?= 85k
BUILDDIR = bin
TOP ?= top
VERILOG ?= $(wildcard *.v)
compile: $(BUILDDIR)/toplevel.bit
prog: $(BUILDDIR)/toplevel.bit
fujprog $^
dfu: $(BUILDDIR)/toplevel.bit
dfu-util -a 0 -D $^ -R
sim: $(BUILDDIR)/sim.out
$^
$(BUILDDIR)/sim.out: $(VERILOG) sim_main.cpp
mkdir -p $(BUILDDIR)
verilator -Wall --cc $(VERILOG) \
--top-module top \
--exe sim_main.cpp \
--build -CFLAGS "-O2 -std=c++17" \
--trace \
--Wno-UNUSEDSIGNAL \
--Wno-UNDRIVEN \
--timing
cp obj_dir/Vtop $@
$(BUILDDIR)/toplevel.json: $(VERILOG)
mkdir -p $(BUILDDIR)
yosys \
-p "read -sv $^" \
-p "hierarchy -top ${TOP}" \
-p "synth_ecp5 -abc9 -json $@" \
$(BUILDDIR)/%.config: $(PIN_DEF) $(BUILDDIR)/toplevel.json
nextpnr-ecp5 --${DEVICE} --package CABGA381 --timing-allow-fail --freq 25 --textcfg $@ --json $(filter-out $<,$^) --lpf $<
$(BUILDDIR)/toplevel.bit: $(BUILDDIR)/toplevel.config
ecppack --compress $^ $@
clean:
rm -rf ${BUILDDIR} obj_dir
.SECONDARY:
.PHONY: compile clean prog dfu sim

397
Verilator_Tests/spi/ulx4m_v002.lpf Normal file
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BLOCK RESETPATHS;
BLOCK ASYNCPATHS;
## ULX4M-LS v0.0.2
# The clock "usb" and "gpdi" sheet
LOCATE COMP "clk_25mhz" SITE "G2";
IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33;
FREQUENCY PORT "clk_25mhz" 25 MHZ;
# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash
# write to FLASH possible any time from JTAG:
# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;
# write to FLASH possible from user bitstream:
SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
## LED indicators "blinkey" and "gpio" sheet
LOCATE COMP "led[3]" SITE "C1";
LOCATE COMP "led[2]" SITE "B3";
LOCATE COMP "led[1]" SITE "B1";
LOCATE COMP "led[0]" SITE "B2";
IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
## Buttons "blinkey" and "gpio" sheet
LOCATE COMP "btn[1]" SITE "C3";
LOCATE COMP "btn[2]" SITE "C2";
IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
## SPI Flash chip "flash" sheet
LOCATE COMP "flash_csn" SITE "R2";
LOCATE COMP "flash_clk" SITE "U3";
LOCATE COMP "flash_mosi" SITE "W2";
LOCATE COMP "flash_miso" SITE "V2";
LOCATE COMP "flash_holdn" SITE "W1";
LOCATE COMP "flash_wpn" SITE "Y2";
#LOCATE COMP "flash_csspin" SITE "AJ3";
#LOCATE COMP "flash_initn" SITE "AG4";
#LOCATE COMP "flash_done" SITE "AJ4";
#LOCATE COMP "flash_programn" SITE "AH4";
#LOCATE COMP "flash_cfg_select[0]" SITE "AM4";
#LOCATE COMP "flash_cfg_select[1]" SITE "AL4";
#LOCATE COMP "flash_cfg_select[2]" SITE "AK4";
IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
## SD card "sdcard", "usb" sheet
LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14 CM4_GPIO12
LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi_GPIO15 CM4_GPIO27
LOCATE COMP "sd_d[0]" SITE "J3"; # sd_dat0_do (MISO) WiFi_GPIO2 CM4_GPIO4
LOCATE COMP "sd_d[1]" SITE "H1"; # sd_dat1_irq WiFi_GPIO4 CM4_GPIO3
LOCATE COMP "sd_d[2]" SITE "K1"; # sd_dat2 WiFi_GPIO12 CM4_GPIO2
LOCATE COMP "sd_d[3]" SITE "K2"; # sd_dat3_csn WiFi_GPIO13 CM4_GPIO14
LOCATE COMP "sd_wp" SITE "P5"; # not connected
LOCATE COMP "sd_cdn" SITE "N5"; # not connected
IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement
IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "sd_pwr_on" SITE "U17"; # J2_5- GN14
IOBUF PORT "sd_pwr_on" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
## Second USB port "US2" going directly into FPGA "usb", "ram" sheet
LOCATE COMP "usb_fpga_dp" SITE "E16"; # same on ULX3S and ULX4M
LOCATE COMP "usb_fpga_dn" SITE "F16"; # same on ULX3S and ULX4M
IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16;
IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16;
LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # single-ended bidirectional same on ULX3S and ULX4M
LOCATE COMP "usb_fpga_bd_dn" SITE "E15"; # single-ended bidirectional same on ULX3S and ULX4M
IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "usb_fpga_pu_dp" SITE "A2"; # pull up/down control
LOCATE COMP "usb_fpga_pu_dn" SITE "A3";
IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
IOBUF PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
LOCATE COMP "usb_fpga_otg_id" SITE "A4";
IOBUF PORT "usb_fpga_otg_id" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "n_extrst" SITE "U16";
IOBUF PORT "n_extrst" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
## JTAG ESP-32 "usb" sheet
# connected to FT231X and ESP-32
# commented out because those are dedicated pins, not directly useable as GPIO
# but could be used by some vendor-specific JTAG bridging (boundary scan) module
#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives
#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits
#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives
#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives
#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
## SDRAM "ram" sheet
LOCATE COMP "sdram_clk" SITE "G19";
LOCATE COMP "sdram_cke" SITE "G20";
LOCATE COMP "sdram_csn" SITE "P18";
LOCATE COMP "sdram_wen" SITE "N20";
LOCATE COMP "sdram_rasn" SITE "M18";
LOCATE COMP "sdram_casn" SITE "N18";
LOCATE COMP "sdram_a[0]" SITE "L19";
LOCATE COMP "sdram_a[1]" SITE "L20";
LOCATE COMP "sdram_a[2]" SITE "M19";
LOCATE COMP "sdram_a[3]" SITE "H17";
LOCATE COMP "sdram_a[4]" SITE "F20";
LOCATE COMP "sdram_a[5]" SITE "F18";
LOCATE COMP "sdram_a[6]" SITE "E19";
LOCATE COMP "sdram_a[7]" SITE "F19";
LOCATE COMP "sdram_a[8]" SITE "E20";
LOCATE COMP "sdram_a[9]" SITE "C20";
LOCATE COMP "sdram_a[10]" SITE "N19";
LOCATE COMP "sdram_a[11]" SITE "D20";
LOCATE COMP "sdram_a[12]" SITE "E18";
LOCATE COMP "sdram_ba[0]" SITE "L18";
LOCATE COMP "sdram_ba[1]" SITE "M20";
LOCATE COMP "sdram_dqm[0]" SITE "P20";
LOCATE COMP "sdram_dqm[1]" SITE "D19";
LOCATE COMP "sdram_d[0]" SITE "U20";
LOCATE COMP "sdram_d[1]" SITE "T20";
LOCATE COMP "sdram_d[2]" SITE "U19";
LOCATE COMP "sdram_d[3]" SITE "T19";
LOCATE COMP "sdram_d[4]" SITE "T18";
LOCATE COMP "sdram_d[5]" SITE "T17";
LOCATE COMP "sdram_d[6]" SITE "R20";
LOCATE COMP "sdram_d[7]" SITE "P19";
LOCATE COMP "sdram_d[8]" SITE "H20";
LOCATE COMP "sdram_d[9]" SITE "J19";
LOCATE COMP "sdram_d[10]" SITE "K18";
LOCATE COMP "sdram_d[11]" SITE "J18";
LOCATE COMP "sdram_d[12]" SITE "H18";
LOCATE COMP "sdram_d[13]" SITE "J16";
LOCATE COMP "sdram_d[14]" SITE "K19";
LOCATE COMP "sdram_d[15]" SITE "J17";
IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
# GPDI differential interface (Video) "gpdi" sheet
LOCATE COMP "gpdi_dp[0]" SITE "F17"; # Blue +
LOCATE COMP "gpdi_dn[0]" SITE "G18"; # Blue -
LOCATE COMP "gpdi_dp[1]" SITE "D18"; # Green +
LOCATE COMP "gpdi_dn[1]" SITE "E17"; # Green -
LOCATE COMP "gpdi_dp[2]" SITE "C18"; # Red +
LOCATE COMP "gpdi_dn[2]" SITE "D17"; # Red -
LOCATE COMP "gpdi_dp[3]" SITE "J20"; # Clock +
LOCATE COMP "gpdi_dn[3]" SITE "K20"; # Clock -
#LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet +
#LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet -
LOCATE COMP "gpdi_cec" SITE "A18";
#LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC
#LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12
IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "gpdi_dp[4]" SITE "B9"; # Blue +
#LOCATE COMP "gpdi_dn[4]" SITE "C10"; # Blue -
LOCATE COMP "gpdi_dp[5]" SITE "A7"; # Green +
#LOCATE COMP "gpdi_dn[5]" SITE "A8"; # Green -
LOCATE COMP "gpdi_dp[6]" SITE "C8"; # Red +
#LOCATE COMP "gpdi_dn[6]" SITE "B8"; # Red -
LOCATE COMP "gpdi_dp[7]" SITE "B11"; # Clock +
#LOCATE COMP "gpdi_dn[7]" SITE "C11"; # Clock -
IOBUF PORT "gpdi_dp[4]" IO_TYPE=LVCMOS33D DRIVE=4;
IOBUF PORT "gpdi_dn[4]" IO_TYPE=LVCMOS33D DRIVE=4;
IOBUF PORT "gpdi_dp[5]" IO_TYPE=LVCMOS33D DRIVE=4;
IOBUF PORT "gpdi_dn[5]" IO_TYPE=LVCMOS33D DRIVE=4;
IOBUF PORT "gpdi_dp[6]" IO_TYPE=LVCMOS33D DRIVE=4;
IOBUF PORT "gpdi_dn[6]" IO_TYPE=LVCMOS33D DRIVE=4;
IOBUF PORT "gpdi_dp[7]" IO_TYPE=LVCMOS33D DRIVE=4;
IOBUF PORT "gpdi_dn[7]" IO_TYPE=LVCMOS33D DRIVE=4;
# wifi - do not use together with CM4 GPIO
LOCATE COMP "wifi_gpio0" SITE "U1";
LOCATE COMP "wifi_gpio2" SITE "K4"; # sd_d0_do (MISO) WiFi GPIO2
LOCATE COMP "wifi_gpio4" SITE "J5"; # sd_d1_irq WiFi GPIO4
LOCATE COMP "wifi_gpio5" SITE "U5"; #
LOCATE COMP "wifi_gpio12" SITE "K5"; # sd_d2 WiFi_GPIO12
LOCATE COMP "wifi_gpio13" SITE "L4"; # sd_d3_csn WiFi_GPIO13
LOCATE COMP "wifi_gpio14" SITE "L5"; # sd_clk WiFi_GPIO14
LOCATE COMP "wifi_gpio15" SITE "N16"; # sd_cmd_di (MOSI) WiFi GPIO15
LOCATE COMP "wifi_gpio19" SITE "P4";
LOCATE COMP "wifi_gpio21" SITE "P17";
LOCATE COMP "wifi_gpio22" SITE "P16";
LOCATE COMP "wifi_gpio25" SITE "L16";
LOCATE COMP "wifi_gpio26" SITE "N17";
LOCATE COMP "wifi_gpio27" SITE "G16";
LOCATE COMP "wifi_gpio33" SITE "H16";
LOCATE COMP "wifi_gpio34" SITE "V4";
LOCATE COMP "wifi_gpio35" SITE "N17";
IOBUF PORT "wifi_gpio0" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio2" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # pull down or drive 0 for esp32 programming
IOBUF PORT "wifi_gpio4" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio5" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio12" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio13" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # pull down or drive 0 for esp32 programming
IOBUF PORT "wifi_gpio14" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio15" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio19" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio21" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio22" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio25" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio26" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio27" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio33" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio34" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_gpio35" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "ftdi_txden" SITE "T1"; # FTDI_TXDEN
LOCATE COMP "LED1_HAT" SITE "N5"; # LED1 on HAT
LOCATE COMP "wifi_en" SITE "U18";# WIFI_EN
LOCATE COMP "ftdi_txd" SITE "N4"; # FTDI_TXD
LOCATE COMP "ftdi_rxd" SITE "N3"; # FTDI_RXD
LOCATE COMP "wifi_txd" SITE "P5"; # WIFI_TXD
LOCATE COMP "wifi_rxd" SITE "V1"; # WIFI_RXD
IOBUF PORT "ftdi_txden" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "LED1_HAT" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "ftdi_txd" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "ftdi_rxd" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "btn[3]" SITE "E3";
LOCATE COMP "btn[4]" SITE "E4";
LOCATE COMP "btn[5]" SITE "E5";
LOCATE COMP "btn[6]" SITE "H5";
LOCATE COMP "btn[0]" SITE "H4";
LOCATE COMP "nc1" SITE "F2";
LOCATE COMP "sw" SITE "G3";
IOBUF PORT "btn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "btn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "btn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "btn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "btn[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "nc1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sw[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
## CM4 GPIO
LOCATE COMP "gpio[0]" SITE "R16"; # SDA0 - WIFI_GPIO21
LOCATE COMP "gpio[1]" SITE "R17"; # SCL0 - WIFI_GPIO22
LOCATE COMP "gpio[2]" SITE "K5"; # SD_D2 - ESP32 SD share
LOCATE COMP "gpio[3]" SITE "J5"; # SD_D1 - ESP32 SD share
LOCATE COMP "gpio[4]" SITE "K4"; # SD_D0 - ESP32 SD share
LOCATE COMP "gpio[5]" SITE "H16"; # WIFI_GPIO33
LOCATE COMP "gpio[6]" SITE "R1"; # BTN1 on HAT
LOCATE COMP "gpio[7]" SITE "P3"; # BTN2 on HAT
LOCATE COMP "gpio[8]" SITE "P4"; # WIFI_GPIO19
LOCATE COMP "gpio[9]" SITE "G16"; # WIFI_GPIO27
LOCATE COMP "gpio[10]" SITE "N17";# WIFI_GPIO26
LOCATE COMP "gpio[11]" SITE "L16";# WIFI_GPIO25
LOCATE COMP "gpio[12]" SITE "C4"; # FPGA TDI do not use - not connected!
LOCATE COMP "gpio[13]" SITE "T1"; # FTDI_TXDEN
LOCATE COMP "gpio[14]" SITE "L4"; # SD_D3 - ESP32 SD share
LOCATE COMP "gpio[15]" SITE "L5"; # SD_CLK - ESP32 SD share
LOCATE COMP "gpio[16]" SITE "B4"; # FPGA TDO do not use - not connected!
LOCATE COMP "gpio[17]" SITE "M17";# WIFI_GPIO35
LOCATE COMP "gpio[18]" SITE "N5"; # LED1 on HAT
LOCATE COMP "gpio[19]" SITE "U1"; # WIFI_GPIO0
LOCATE COMP "gpio[20]" SITE "E4"; # FPGA TCK do not use - not connected!
LOCATE COMP "gpio[21]" SITE "D5"; # FPGA TMS do not use - not connected!
LOCATE COMP "gpio[22]" SITE "U18";# WIFI_EN
LOCATE COMP "gpio[23]" SITE "N4"; # FTDI_TXD
LOCATE COMP "gpio[24]" SITE "N3"; # FTDI_RXD
LOCATE COMP "gpio[25]" SITE "P5"; # WIFI_TXD
LOCATE COMP "gpio[26]" SITE "V1"; # WIFI_RXD
LOCATE COMP "gpio[27]" SITE "N16";# SD_CMD - ESP32 SD share
IOBUF PORT "gpio[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[16]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[17]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[18]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[19]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[20]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[21]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[22]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[23]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[24]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[25]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[26]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpio[27]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
## DSI
#
LOCATE COMP "dsiRX0_dp[0]" SITE "B12"; # Clk +
LOCATE COMP "dsiRX0_dn[0]" SITE "C12"; # Clk -
LOCATE COMP "dsiRX0_dp[1]" SITE "A12"; # DSI RX D0 +
LOCATE COMP "dsiRX0_dn[1]" SITE "A13"; # DSI RX D0 -
LOCATE COMP "dsiRX0_dp[2]" SITE "B13"; # DSI RX D1 +
LOCATE COMP "dsiRX0_dn[2]" SITE "C13"; # DSI RX D1 -
LOCATE COMP "dsiTX0_dp[0]" SITE "D12"; # Clk +
LOCATE COMP "dsiTX0_dn[0]" SITE "E12"; # Clk -
LOCATE COMP "dsiTX0_dp[1]" SITE "D13"; # DSI TX D0 +
LOCATE COMP "dsiTX0_dn[1]" SITE "E13"; # DSI TX D0 -
LOCATE COMP "dsiTX0_dp[2]" SITE "A14"; # DSI TX D1 +
LOCATE COMP "dsiTX0_dn[2]" SITE "C14"; # DSI TX D1 -
IOBUF PORT "dsiRX0_dp[0]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiRX0_dn[0]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiRX0_dp[1]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiRX0_dn[1]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiRX0_dp[2]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiRX0_dn[2]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiTX0_dp[0]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiTX0_dp[0]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiTX0_dp[1]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiTX0_dp[1]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiTX0_dp[2]" IO_TYPE=LVCMOS12 ;
IOBUF PORT "dsiTX0_dp[2]" IO_TYPE=LVCMOS12 ;
## PROGRAMN (reload bitstream from FLASH, exit from bootloader)
# PCB v2.0.5 and higher
LOCATE COMP "user_programn" SITE "M4";
IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5)
# on PCB v1.7 shutdown is not connected to FPGA
LOCATE COMP "shutdown" SITE "G16"; # FPGA receives
IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;

858
Verilator_Tests/spi/wave.vcd Normal file
View File

@@ -0,0 +1,858 @@
$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module TOP $end
$var wire 1 * clk_25mhz $end
$var wire 1 + spi_clk $end
$var wire 1 , spi_mosi $end
$var wire 1 - spi_miso $end
$var wire 1 . spi_cs $end
$scope module top $end
$var wire 1 * clk_25mhz $end
$var wire 1 + spi_clk $end
$var wire 1 , spi_mosi $end
$var wire 1 - spi_miso $end
$var wire 1 . spi_cs $end
$var wire 8 # miso [7:0] $end
$var wire 8 / mosi [7:0] $end
$var wire 1 $ busy $end
$var wire 1 % start $end
$scope module spimaster0 $end
$var wire 1 * clk $end
$var wire 1 + spi_clk $end
$var wire 1 % start $end
$var wire 8 / data_out [7:0] $end
$var wire 1 , spi_mosi $end
$var wire 8 # data_in [7:0] $end
$var wire 1 - spi_miso $end
$var wire 1 $ busy $end
$var wire 1 . spi_cs $end
$var wire 4 & bit_cnt [3:0] $end
$var wire 8 ' shift_reg_in [7:0] $end
$var wire 8 ( shift_reg_out [7:0] $end
$var wire 2 ) state [1:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
b00000000 #
0$
0%
b0000 &
b00000000 '
b00000000 (
b00 )
1*
0+
0,
0-
1.
b01101011 /
#20
0*
#40
1%
1*
#60
0*
#80
0%
b01101011 (
b01 )
1*
#100
0*
#120
1$
1%
b10 )
1*
0.
#140
0*
#160
0%
b11010110 (
1*
1+
#180
0*
#200
b0001 &
1*
0+
#220
0*
#240
b10101100 (
1*
1+
1,
#260
0*
#280
b0010 &
1*
0+
#300
0*
#320
b01011000 (
1*
1+
#340
0*
#360
b0011 &
1*
0+
#380
0*
#400
b10110000 (
1*
1+
0,
#420
0*
#440
b0100 &
1*
0+
#460
0*
#480
b01100000 (
1*
1+
1,
#500
0*
#520
b0101 &
1*
0+
#540
0*
#560
b11000000 (
1*
1+
0,
#580
0*
#600
b0110 &
1*
0+
#620
0*
#640
b10000000 (
1*
1+
1,
#660
0*
#680
b0111 &
1*
0+
#700
0*
#720
b00000000 (
1*
1+
#740
0*
#760
b1000 &
b11 )
1*
0+
#780
0*
#800
b00 )
1*
1.
#820
0*
#840
0$
1*
#860
0*
#880
1%
1*
#900
0*
#920
0%
b0000 &
b01101011 (
b01 )
1*
#940
0*
#960
1$
1%
b10 )
1*
0.
#980
0*
#1000
0%
b11010110 (
1*
1+
0,
#1020
0*
#1040
b0001 &
1*
0+
#1060
0*
#1080
b10101100 (
1*
1+
1,
#1100
0*
#1120
b0010 &
1*
0+
#1140
0*
#1160
b01011000 (
1*
1+
#1180
0*
#1200
b0011 &
1*
0+
#1220
0*
#1240
b10110000 (
1*
1+
0,
#1260
0*
#1280
b0100 &
1*
0+
#1300
0*
#1320
b01100000 (
1*
1+
1,
#1340
0*
#1360
b0101 &
1*
0+
#1380
0*
#1400
b11000000 (
1*
1+
0,
#1420
0*
#1440
b0110 &
1*
0+
#1460
0*
#1480
b10000000 (
1*
1+
1,
#1500
0*
#1520
b0111 &
1*
0+
#1540
0*
#1560
b00000000 (
1*
1+
#1580
0*
#1600
b1000 &
b11 )
1*
0+
#1620
0*
#1640
b00 )
1*
1.
#1660
0*
#1680
0$
1*
#1700
0*
#1720
1%
1*
#1740
0*
#1760
0%
b0000 &
b01101011 (
b01 )
1*
#1780
0*
#1800
1$
1%
b10 )
1*
0.
#1820
0*
#1840
0%
b11010110 (
1*
1+
0,
#1860
0*
#1880
b0001 &
1*
0+
#1900
0*
#1920
b10101100 (
1*
1+
1,
#1940
0*
#1960
b0010 &
1*
0+
#1980
0*
#2000
b01011000 (
1*
1+
#2020
0*
#2040
b0011 &
1*
0+
#2060
0*
#2080
b10110000 (
1*
1+
0,
#2100
0*
#2120
b0100 &
1*
0+
#2140
0*
#2160
b01100000 (
1*
1+
1,
#2180
0*
#2200
b0101 &
1*
0+
#2220
0*
#2240
b11000000 (
1*
1+
0,
#2260
0*
#2280
b0110 &
1*
0+
#2300
0*
#2320
b10000000 (
1*
1+
1,
#2340
0*
#2360
b0111 &
1*
0+
#2380
0*
#2400
b00000000 (
1*
1+
#2420
0*
#2440
b1000 &
b11 )
1*
0+
#2460
0*
#2480
b00 )
1*
1.
#2500
0*
#2520
0$
1*
#2540
0*
#2560
1%
1*
#2580
0*
#2600
0%
b0000 &
b01101011 (
b01 )
1*
#2620
0*
#2640
1$
1%
b10 )
1*
0.
#2660
0*
#2680
0%
b11010110 (
1*
1+
0,
#2700
0*
#2720
b0001 &
1*
0+
#2740
0*
#2760
b10101100 (
1*
1+
1,
#2780
0*
#2800
b0010 &
1*
0+
#2820
0*
#2840
b01011000 (
1*
1+
#2860
0*
#2880
b0011 &
1*
0+
#2900
0*
#2920
b10110000 (
1*
1+
0,
#2940
0*
#2960
b0100 &
1*
0+
#2980
0*
#3000
b01100000 (
1*
1+
1,
#3020
0*
#3040
b0101 &
1*
0+
#3060
0*
#3080
b11000000 (
1*
1+
0,
#3100
0*
#3120
b0110 &
1*
0+
#3140
0*
#3160
b10000000 (
1*
1+
1,
#3180
0*
#3200
b0111 &
1*
0+
#3220
0*
#3240
b00000000 (
1*
1+
#3260
0*
#3280
b1000 &
b11 )
1*
0+
#3300
0*
#3320
b00 )
1*
1.
#3340
0*
#3360
0$
1*
#3380
0*
#3400
1%
1*
#3420
0*
#3440
0%
b0000 &
b01101011 (
b01 )
1*
#3460
0*
#3480
1$
1%
b10 )
1*
0.
#3500
0*
#3520
0%
b11010110 (
1*
1+
0,
#3540
0*
#3560
b0001 &
1*
0+
#3580
0*
#3600
b10101100 (
1*
1+
1,
#3620
0*
#3640
b0010 &
1*
0+
#3660
0*
#3680
b01011000 (
1*
1+
#3700
0*
#3720
b0011 &
1*
0+
#3740
0*
#3760
b10110000 (
1*
1+
0,
#3780
0*
#3800
b0100 &
1*
0+
#3820
0*
#3840
b01100000 (
1*
1+
1,
#3860
0*
#3880
b0101 &
1*
0+
#3900
0*
#3920
b11000000 (
1*
1+
0,
#3940
0*
#3960
b0110 &
1*
0+
#3980
0*
#4000
b10000000 (
1*
1+
1,
#4020
0*
#4040
b0111 &
1*
0+
#4060
0*
#4080
b00000000 (
1*
1+
#4100
0*
#4120
b1000 &
b11 )
1*
0+
#4140
0*
#4160
b00 )
1*
1.
#4180
0*
#4200
0$
1*
#4220
0*
#4240
1%
1*
#4260
0*
#4280
0%
b0000 &
b01101011 (
b01 )
1*
#4300
0*
#4320
1$
1%
b10 )
1*
0.
#4340
0*
#4360
0%
b11010110 (
1*
1+
0,
#4380
0*
#4400
b0001 &
1*
0+
#4420
0*
#4440
b10101100 (
1*
1+
1,
#4460
0*
#4480
b0010 &
1*
0+
#4500
0*
#4520
b01011000 (
1*
1+
#4540
0*
#4560
b0011 &
1*
0+
#4580
0*
#4600
b10110000 (
1*
1+
0,
#4620
0*
#4640
b0100 &
1*
0+
#4660
0*
#4680
b01100000 (
1*
1+
1,
#4700
0*
#4720
b0101 &
1*
0+
#4740
0*
#4760
b11000000 (
1*
1+
0,
#4780
0*
#4800
b0110 &
1*
0+
#4820
0*
#4840
b10000000 (
1*
1+
1,
#4860
0*
#4880
b0111 &
1*
0+
#4900
0*
#4920
b00000000 (
1*
1+
#4940
0*
#4960
b1000 &
b11 )
1*
0+
#4980
0*
#4999