that again

Max10_RT/Max10_RT.qpf

@@ -2,4 +2,4 @@ QUARTUS_VERSION = "17.1"
 DATE = "13:14:16  February 14, 2018"
 
 # Revisions
-PROJECT_REVISION = "Max10_VGA"
+PROJECT_REVISION = "Max10_RT"

Max10_RT/Max10_RT.qsf

@@ -45,6 +45,12 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk12m
 
 
 set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb -section_id tb
+set_global_assignment -name EDA_TEST_BENCH_FILE top_tb.sv -section_id tb
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_acc.tcl
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_button.tcl
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pins/assignment_gpio.tcl
@@ -56,11 +62,6 @@ set_global_assignment -name QIP_FILE PLL.qip
 set_global_assignment -name SYSTEMVERILOG_FILE top.sv
 set_global_assignment -name SYSTEMVERILOG_FILE top_tb.sv
 set_global_assignment -name SYSTEMVERILOG_FILE vga_controller.sv
-set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
-set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb -section_id eda_simulation
-set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation
-set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb
-set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb -section_id tb
-set_global_assignment -name EDA_TEST_BENCH_FILE top_tb.sv -section_id tb
 set_global_assignment -name SYSTEMVERILOG_FILE vga_test_screen.sv
+set_global_assignment -name SYSTEMVERILOG_FILE raytracer.sv
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Max10_RT/raytracer.sv

@@ -0,0 +1,8 @@
+module Raytracer(
+	input wire pixel_clk,
+	input reg [10:0] x,
+	input reg [10:0] y,
+	output reg [2:0] rgb
+);
+
+endmodule

Max10_RT/raytracer.sv.bak

@@ -0,0 +1,3 @@
+module Raytracer();
+
+endmodule

Max10_Raytracer/top.sv.bak

@@ -1,42 +0,0 @@
-module max1000_template (
-	// Main 12M clock
-	input logic clk12m,
-
-	// Accelerometer
-	output logic acc_sclk,
-	output logic acc_mosi,
-	input  logic acc_miso,
-	output logic acc_cs,
-	input  logic acc_int1,
-	input  logic acc_int2,
-
-	// Onboard button
-	input  logic btn,
-
-	// Header GPIO
-	inout  logic [14:0] gpio_d,
-	input  logic  [7:0] gpio_a,
-
-	// Onboard LEDs
-	output logic  [8:1] led,
-
-	// PMOD header
-	inout  logic  [8:1] pmod,
-
-	// Onboard RAM
-	output logic        ram_clk,
-	inout  logic [15:0] ram_data,
-	output logic [13:0] ram_addr,
-	output logic  [1:0] ram_dqm,
-	output logic  [1:0] ram_bs,
-	output logic        ram_cke,
-	output logic        ram_ras,
-	output logic        ram_cas,
-	output logic        ram_we,
-	output logic        ram_cs
-);
-
-// This is the top module, enter your design here
-// Happy HDL :]
-
-endmodule

Max10_Raytracer/top_tb.sv.bak

@@ -1,24 +0,0 @@
-`timescale 1 ns / 100 ps
-
-module tb();
-	reg clk = 1'b0;
-	
-	reg [14:0] v_gpio_d;
-	reg [8:1] v_led;
-	
-	VGA_Controller VGA_Controller_Inst(
-		.pixel_clk(clk),
-		.gpio_d(v_gpio_d)
-	);
-
-	// 25MHz clock
-	always #5 clk <= ~clk;
-	
-	
-	initial begin
-		$display($time, " Starting the Simulation");
-		#1000
-		$finish();
-	end
-	
-endmodule

Max10_Raytracer/vga_controller.sv.bak

@@ -1,8 +0,0 @@
-module VGA_Controller(
-	input wire pixel_clk,
-	inout  logic [14:0] gpio_d,
-	output logic  [8:1] led
-};
-
-
-endmodule

Max10_Raytracer/vga_test_screen.sv.bak

@@ -1,5 +0,0 @@
-VGA_Test_Screen(
-	input wire [10:0] scan_pos_x,
-	input wire [10:0] scan_pos_y,
-	output wire [2:0] rgb,
-);

Max10_VGA/top.sv.bak

@@ -1,42 +0,0 @@
-module max1000_template (
-	// Main 12M clock
-	input logic clk12m,
-
-	// Accelerometer
-	output logic acc_sclk,
-	output logic acc_mosi,
-	input  logic acc_miso,
-	output logic acc_cs,
-	input  logic acc_int1,
-	input  logic acc_int2,
-
-	// Onboard button
-	input  logic btn,
-
-	// Header GPIO
-	inout  logic [14:0] gpio_d,
-	input  logic  [7:0] gpio_a,
-
-	// Onboard LEDs
-	output logic  [8:1] led,
-
-	// PMOD header
-	inout  logic  [8:1] pmod,
-
-	// Onboard RAM
-	output logic        ram_clk,
-	inout  logic [15:0] ram_data,
-	output logic [13:0] ram_addr,
-	output logic  [1:0] ram_dqm,
-	output logic  [1:0] ram_bs,
-	output logic        ram_cke,
-	output logic        ram_ras,
-	output logic        ram_cas,
-	output logic        ram_we,
-	output logic        ram_cs
-);
-
-// This is the top module, enter your design here
-// Happy HDL :]
-
-endmodule

Max10_VGA/top_tb.sv.bak

@@ -1,24 +0,0 @@
-`timescale 1 ns / 100 ps
-
-module tb();
-	reg clk = 1'b0;
-	
-	reg [14:0] v_gpio_d;
-	reg [8:1] v_led;
-	
-	VGA_Controller VGA_Controller_Inst(
-		.pixel_clk(clk),
-		.gpio_d(v_gpio_d)
-	);
-
-	// 25MHz clock
-	always #5 clk <= ~clk;
-	
-	
-	initial begin
-		$display($time, " Starting the Simulation");
-		#1000
-		$finish();
-	end
-	
-endmodule

Max10_VGA/vga_controller.sv.bak

@@ -1,8 +0,0 @@
-module VGA_Controller(
-	input wire pixel_clk,
-	inout  logic [14:0] gpio_d,
-	output logic  [8:1] led
-};
-
-
-endmodule

Max10_VGA/vga_test_screen.sv.bak

@@ -1,5 +0,0 @@
-VGA_Test_Screen(
-	input wire [10:0] scan_pos_x,
-	input wire [10:0] scan_pos_y,
-	output wire [2:0] rgb,
-);